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i2c bus

Discussion in 'General Electronics Discussion' started by Leond95, Nov 30, 2018.

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  1. Leond95

    Leond95

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    Nov 30, 2018
    Hi everyone,

    pleasecan someone explain to me why thr SDL signal have this forme, as you can see on the second picture the signal can take 0 and 1 simultaneously


    thanks
     

    Attached Files:

  2. kellys_eye

    kellys_eye

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    Jun 25, 2010
    That (poor) image only illustrates the two POSSIBLE states of data - 1 or 0. They don't happen simultaneously.
     
  3. Leond95

    Leond95

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    Nov 30, 2018
    please can you explain more about the form of the SDL signal because I didn't quit understand
     
  4. kellys_eye

    kellys_eye

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    Jun 25, 2010
    There are many tutorials on the I2C bus that you could access:

    ...however the diagrams you posted show how the clock signal (SCL) corresponds to the individual data bits in the data signal (SDA) where the status of SDA is read at the 'top' (flat part) of the clock (SCL) signal.

    The data could be EITHER zero or one - that's why the image shows 'both' states - it doesn't assume any particular condition when explaining how the data and clock signals relate to each other.
     
  5. Harald Kapp

    Harald Kapp Moderator Moderator

    9,639
    2,014
    Nov 17, 2011
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