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I/O signal conditioning question

Discussion in 'Electronic Design' started by John S. Gaglione, Apr 5, 2007.

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  1. Greetings Group:
    I am working on the interface between an LCD display and
    a PIC 16F877A.

    The display multiplexes its "BUSY" signal on the same pin as
    the 8th data bit.

    My problem is that the PIC input pin cannot see the 2.4v BUSY signal.

    I have tried buffering the signal through 2 gates on a 74LS04.
    The PIC now can see this fine, but when the LCD switches the pin
    over to read data it floats and the '04 gates turn on.
    This causes the LCD to read the 8th bit "On" all the time,
    interfering with the character data. I tried several
    resistors to force the gate input down, but the PIC's data
    doesn't get through reliably.

    I found that this will work if I connect the signal directly
    between the PIC and the LCD, and also connect it to the base
    of a PNP transistor with a PCB mount speaker (piezo?),
    connected between the Collector and +5, and Emitter to GND.

    I don't want to keep the speaker in the circuit, because it seems
    to draw a lot of current, and I don't understand why it works.

    Any other suggestions for increasing the voltage of my BUSY
    signal, without drowning out the signal from the PIC direction?

    Thanks

    John
     
  2. John  Larkin

    John Larkin Guest

    Try just a 1K pullup resistor to the Vcc of the PIC.

    John
     
  3. How do you know it is only 2.4V? What is the LCD display Vdd? What is
    the MPU Vdd? Which port are you using for the data bits? Most of the
    port pins use TTL-like levels when you use 5V Vdd, but PORTC ohn that
    part has ST inputs, and requires 0.8Vdd to see a logic 1. Do you
    actually need to read the BUSY signal or can you just use timing?
    Most LCD controller chips are CMOS and have outputs that swing from 0V
    to VDD.

    If I was to make a WAG as to what is wrong, I'd guess that you have
    misunderstood the controller datasheet and the BUSY output is
    open-drain, and thus requires a pullup resistor (something like 10K)
    to your Vdd.
     
  4. That's weird. I've always read the busy flag and every LCD I've ever used
    (at least 5 completely different models), they've all worked ok. Are you
    sure the output is only 2.4V? What Vcc are you using for the LCD? Are you
    setting the whole PORT to input mode, or only the busy pin? You are
    toggling the R/W line correctly, right? 2.4V sounds suspicously like an
    oscillating pin, have you looked with a scope?
     
  5. LCD Specs say Vdd +2.4v. Vdd is +5v. Measured on o'scope as 2.4v, so Vdd
    +2.4 may be a typo for Vss +2.4. MPU Vdd is +5v, same as LCD.
    Data bits to LCD are on port D. I've set TRISE:4 (PSPMODE) to 1, hoping
    to get PORTD to be TTL inputs but it still won't see the BUSY signal.
    Please pardon my limited electronics knowledge, If I set PSPMODE, with
    a 10K pull-up resistor from Vdd to PORTD:7, the "low" level bumps up to
    about 2V. With PSPMODE cleared (Schmidt Trigger inputs), the pull-up
    does not affect the "low", but raises the "hi" a bit.(2.4v to 2.5v). Is
    this the expected behaviour?

    Yes, I could ignore the busy signal and just burn cycles to get it to
    work, but I want to do it the right way.

    With the busy signal connected with the piezo speaker, I sent the display
    40 million characters without dropping one. Using timing, I see a
    character out-of-place every 5000.

    The display is a S28297 made by IEE (Industrial Electronic Engineers)
    Inc. from Van Nuys CA. The spec. sheet is dated 1983.
     
  6. Thanks for the reply.

    The 2.4v measurement is from the scope. I'm actually only setting
    the one pin to input mode to read the busy signal. I just now tried
    setting all 8 to input and it's the same. How do I tell if it's
    oscillating? It looks like a (sort-of) square wave...
     
  7. Rich Webb

    Rich Webb Guest

    IIRC, you must set R/~W, reset RS, *and then* pulse E; it's more than
    setting one pin. The bits from the LCD module will be valid shortly
    after the rising edge of E (see data sheet for timing). If you're in
    four-bit mode, do this twice for each byte to be read. You may also
    want pull-ups if the minimum logic "1" from the module is less than
    the guaranteed logic threshold for your processor.
     
  8. Hi Rich - By "setting one pin" above I meant that I was only changing
    one pin (B7/BUSY) to input mode when I was ready to read the LCD's
    BUSY/READY state. I'm pretty sure I have the bit flip protocol and
    timing right: The display runs like a champ when my PIC can see the busy
    signal.

    I tried a 10k pull-up. The peaks went from 2.4 to 2.5v, and the PIC
    still couldn't see it.
     
  9. Jamie

    Jamie Guest

    how about a Tristate buffer ?
     
  10. Jamie

    Jamie Guest

    getting back to your first post. what about a common emitter to drive
    the PIC input, use a R from the busy line to drive the transistor into
    saturation which will pull down the PIC input.
    there will be no signal leaking back on your display information that
    way and you'll get your amplified logic signal, inverted how ever.
    collector to PIC input, emitter to common. base via a resistor to the
    busy line.
     
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