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how to stick read write cycle in SRAM

Discussion in 'Electronic Design' started by [email protected], Jul 24, 2007.

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  1. Guest

    I want control the read and write (SRAM single data port AT60142) with
    FPGA
    link http://www.atmel.com/dyn/resources/prod_documents/doc7726.pdf
    but I want stick a read cycle and write cycle in the SAME adress See
    below

    CS ----\_________________/------
    RD ----\_______/-----------------
    WR -----------------\________/-----------
    data ----Z--<--data-->Z

    The data sheet indicate the data still on the bus 8ns after the RD
    raising edge.
    But i m problem with (tGHQZ : time OE high to high Z)
    I think, i can't write with WR falling edge juste after read.
    According your experience
    Can I do that?
     
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