Connect with us

How to reduce existing phase noise

Discussion in 'Electronic Design' started by Erikk, Mar 22, 2005.

Scroll to continue with content
  1. Erikk

    Erikk Guest

    If a clock signal to an A/D has too much phase noise, degrading the
    SNR of the A/D, is there some way to reduce the phase noise before it
    is applied to the ADC?

    I was thinking about using a PLL but I wasn't sure if the output phase
    noise can be lower than the input phase noise.
     
  2. John Larkin

    John Larkin Guest


    It certainly can.

    A lot depends on the spectrum of the jitter. If it's fast
    cycle-to-cycle jitter, just an LC or a more serious bandpass filter
    and a good comparator may be all you need. If it's closer-in phase
    noise (close in the frequency domain, equivalent to slower timing
    drift in time) you might need a PLL with a good crystal oscillator.

    Got any more details... clock rate, nature of the jitter, signal being
    digitized, stuff like that?

    John
     
  3. Erikk

    Erikk Guest

    Hi John,

    The signal is generated in the following way.
    A received 315 MHz unmodulated carrier is fed to a SAW filter, LNA,
    limiting amp, PECL receiver, div by 2 counter, PLL (ADF4360-8).

    Basically, the 315MHz carrier is amplified, then its frequency divided
    in half to 167.5MHz, which is fed to the reference pin of the PLL
    chip. The PLL is set up to multiply by 33/26 so the output frequency
    is about 200MHz.

    A simulation program from Analog Devices (simPLL) gives me acceptable
    jitter of about 2ps rms, if the reference clock is assumed to have
    zero phase noise. In my case, since the reference clock is derived
    from -80dBm 315MHz carrier, I think its phase noise can be quite high
    although I have no idea how to quantify it.

    The output of the PLL is used to clock an 8-bit 200Ms/s ADC. It is
    not built yet but I am concerned with the phase noise in the PLL
    reference clock. So I am wondering how to reduce the phase noise of
    the PLL output assuming the incoming reference has high phase noise.

    Thanks.
     
  4. That is conceivable, depending on what spectrum the
    noise has, (as Mr. Larkin mentioned), and many more
    specifics than you have related. Incoming frequency
    range, your ADC ENOB (in a decent eval setup),
    and what spectrum processing is done to the samples
    (or your whole phase noise requirement) should all
    influence the design of that patch.

    That approach can be difficult or impossible to pull off,
    or more costly than the system approach. (More later.)
    It's like other noise problems. You can use a PLL
    as a filter, but it can add its own noise. Whether
    the result is better depends on what got filtered
    out and what got added.

    The approach I have seen work reliably is: Start
    with a sufficiently pure source. Distribute it with
    careful attention to analog signaling issues. Process
    it with the same care. Do not think of it as a mere
    "digital" signal, intact if 1's and 0's get through,
    unless precise clock edge placement is immaterial.
    (Your ADC's SNR suggests it does matter.)
     
  5. Fred Bloggs

    Fred Bloggs Guest

    Oh yeah- what exactly are those "many more specifics"- give us a rundown..

    Patch? Patch? Hmmm- never have heard anyone refer to improving sampling
    clock phase noise as a "patch".
    Wouldn't that "patch" be the system approach? You really are a
    windbag....you have to pretty dumb to think people don't see you are
    total fake , fraud, generalist moron with no working knowledge whatsoever.
    hey everybody- read that non-informational crock of sh_t- is that a bs
    dodge or what?
    Oooh- well that makes it easy doesn't it- especially when you have an
    unlimited government budget...the OP asked about approaches to improving
    the phase noise of an existing source- and not a bunch of bs about
    identifying a new one.
    People who know what they're doing don't have issues- why don't
    enumerate some of those "signaling issues"- what are they?- what are the
    most common ones?
    Process it with care? Like what are you talking about here?
    Sounds like you're scolding the OP for your flawed approach. And this
    crap about "precise clock edge placement is immaterial" just makes no
    sense in a discussion about jitter-HAHAHAHAHAHAHAA- you do know that
    A/D's sample on a clock edge, right? You know this don't you? You think
    it integrates the waveform or something and sample jitter is an analog
    average thing or something? Hey, if you don't know what you're talking
    then maybe you should just shut the hell up, huh? Think that will work?
     
  6. Fred Bartoli

    Fred Bartoli Guest

    A patch sometimes helps one stop smoking. So it might also help to reduce
    the nose phase.
     
  7. Guest

    Sure it can. But you probably want to think in terms of a low jitter
    voltage controlled oscillator in the phase-locked loop - something like
    a voltage controlled cyrstal oscillator, which can only be pulled over
    a very narrow range of frequencies.

    If the clock for the A/D converter originates in a crystal-controlled
    oscillator, this might be practical.

    If you can get at the path from the original oscillator to the A/D
    converter, you'd probably be better off getting rid of the jitter
    there.
     
  8. Fred Bloggs

    Fred Bloggs Guest

    If the 200MHz A/D clock is to remain constant in frequency and the
    carrier serves merely for phase synchronization purposes of coherent
    demodulation, then there are many reference designs based on "dual loop"
    VCXO based PLL that are the most impervious to reference clock jitter
    and drop out due to low receive SNR. You will find volumes of reference
    material on this in the high speed serial communications literature.
     
  9. Mark

    Mark Guest

    yes a pll may reduce phase noise, it depends on the what kind of phase
    noise is on the input and what kind of vco you can use in the pll and
    what the pll loop bw is.

    in general .....

    the phase noise out of a pll will be the same as the phase noise of the
    vco for offset frequencies above the pll loop band width.

    and

    the phase noise oput of a pll will be the same as the input reference
    for offset frerquencies below the pll loop bandwidth

    depending on your exact problem, a crystal filter can also be used to
    reduce phase noise, if the clock is stable and the phase noise is at a
    high offset.

    or you can try to reduce the phase noise at the source...

    gice us some more details

    Mark
     
  10. John Larkin

    John Larkin Guest

    Sounds interesting. Can the local oscillator be a crystal, a VCXO? If
    so, and if the carrier is processsed correctly up to the phase
    detector, a couple of ps RMS should be doable, and the loop bandwidth
    can be small, in the low KHz, which hides a lot of sins.

    John
     
  11. Erikk

    Erikk Guest

    I left out one important detail.....

    The goal is to generate exactly the same frequency clocks at multiple
    locations which is why the "reference" clock is transmitted as 315MHz
    carrier. I need approximately 200 MHz clock signals at multiple
    locations. The absolute frequency is not important but the
    frequencies at multiple locations must be identical, within 1Hz.

    So I guess the thing to do is keep what I have but utilize a vcxo in
    the PLL rather than a vco to keep the phase noise down. That makes
    sense to me.

    Can anyone give specific parts that I can use? (PLL, VCXO) Again, the
    output frequency is about 200MHz, the input reference frequency is
    157.5MHz. The PLL needs to multiply the input by 33/26.

    Thanks to everyone.
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-