Tony said:
Conceptually intriguing, but as a beginner in programmable logic, even
the lowly
adder still holds my interest. And it doesn't seem that any
alternative to the 3
stage adder will take very much less resources or stages.
This nut can be cracked with a 5ns conversion, and with an obtainable
device, if you take it one bit at a time. Here is one way it can be done:
If you start with two 1 of 16 decoders, each operating on half the input
byte, then you end up with two sets of outputs, say DU4, DU3, DU2, DU1,
DU0, and DL4, DL3, DL2, DL1, and DL0 with obvious notation DXn means n
bits are "1" in nibble X. Then the final output can be derived like so:
F7=DU4.DL3+DU3.DL4
F6=DU4.DL2+DU3.DL3+DU2.DL4
F5=DU4.DL1+DU3.DL2+DU2.DL3+DU1.DL4
F4=DU4.DL0+DU3.DL1+DU2.DL2+DU1.DL3+DU0.DL4
F3=DU3.DL0+DU2.DL1+DU1.DL2+DU0.DL3
F2=DU2.DL0+DU1.DL1+DU0.DL2
F1=DU1.DL0+DU0.DL1
-and this is encoded into binary as [ OUT2 OUT1 OUT 0]:
OUTO=F7+F5+F3+F1
OUT1=F7+F6+F3+F2
OUT2=F7+F6+F5+F4
The 1 of 16 decoder operating on [ B3 B2 B1 B0 ] would look something like:
Please view in a fixed-width font such as Courier.
B1
B3 \ B0
B2 \ 00 01 11 10
+-----+-----+-----+-----+
00 | 0| 1| 3| 2|
| D0 | D1 | D2 | D1 |
+-----+-----+-----+-----+
01 | 4| 5| 7| 6|
| D1 | D2 | D3 | D2 |
+-----+-----+-----+-----+
11 | 12| 13| 15| 14|
| D2 | D3 | D4 | D3 |
+-----+-----+-----+-----+
10 | 8| 9| 11| 10|
| D1 | D2 | D3 | D2 |
+-----+-----+-----+-----+
__ __ __ __
D0= B3.B2.B1.B0
__ __ __ __ __ __ __
D1= B3.B2.(B1.B0+B1.B0)+B3.B2.B1.B0
__ __ __ __ __ __ __ __ __ __
D2= B3.B2.B1.B0+B3.B2.(B1.B0+B1.B0)+B3.B2.B1.B0+B3.B2.(B1.B0+B1.B0)
__ __ __ __
D3=B3.B2.B1.B0+B3.B2.(B1.B0+B1.B0)+B3.B2.B1.B0
D4=B3.B2.B1.B0
-so the maximum complexity is 6 minterms with D2.
Then this diagram looks like so:
Please view in a fixed-width font such as Courier.
b b b b b b b b
7 6 5 4 3 2 1 0
/ / / / \ \ \ \
+----------- ---------+
| |
/4 /4
| |
+---------------------+ +--------------------+
| | | |
| DECODER | | DECODER |
| | | |
| DU4 DU3 DU2 DU1 DU0 | |DL4 DL3 DL2 DL1 DL0 |
+---------------------+ +--------------------+
| 5 5 |
+----/----+ +-----/-----+
| |
+-----------------------+
| |
| LOGIC COMBINE |
| |
| F7 F6 F5 F4 F3 F2 F1 |
+-----------------------+
7|
/
|
+----------------------+
| |
| BINARY ENCODE |
| |
+----------------------+
|
|
\|/
3-BIT BINARY
[ OUT2 OUT1 OUT0 ]
So it's down to three gate delays...simple array logic with plain
combinatorial feedthrough- no interstage pipelining/synchronization
required. I leave it to you to double check the equations.