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How to convert VHDL / Verilog code to layout?

Discussion in 'CAD' started by boki, Feb 2, 2004.

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  1. boki

    boki Guest

    Hi, All:

    Could you please tell me or give me some hint to convert VHDL /
    Verilog code to layout?.

    Thanks a lot!

  2. Russ

    Russ Guest

    In a nutshell:
    o Run synthesis
    o floorplanning
    o timing analysis
    o library create
    o formal verification
    o place & route / Clock
    o signal integrity
    o Design for Test
    o Extraction
    o DRC/LVS
    o Tape-out (priceless!!!!)
  3. boki

    boki Guest

    Thank you very much.

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