Could you please tell me or give me some hint to convert VHDL /
Verilog code to layout?.
Boki.
This is a bit like asking:
Could you please give me a complete college education in an email thread?
Here are some of the basic steps:
- Create a test bench that stimulates the Verilog HDL or VHDL code correctly;
- Functionally simulate the Verilog HDL or VHDL code until it works for you;
- Synthesize the Verilog HDL or VHDL to gates (using any standard cell library);
- Place those gates into a physical layout using any Place & Route tool;
- Route between those gates using same Place & Route tool (e.g., SOC Encounter);
- Handle power grid, signal intgegrity, timing, and area constraints;
- Add design for manufacturing (e.g., scan chain, test points, etc.);
- Add I/O pads & texted bond pads (pin-grid-array anyone?);
- Physically verify design rules (DRC) & electrical correctness (LVS);
- Parasitically extract & back annotate into your original netlist;
- Functionally resimulate to your satisfaction (meeting specifications);
- etc.
Folks. Did I skip anything major?
Polly
P.S. Whom do you work for? I have a stack of resumes from QUALIFIED people
who can do that job above without asking the questions you ask.
