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How to convert VHDL / Verilog code to layout?

Discussion in 'Electronic Basics' started by boki, Feb 2, 2004.

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  1. boki

    boki Guest

    Hi, All:

    Could you please tell me or give me some hint to convert VHDL /
    Verilog code to layout?.

    Thanks a lot!

  2. This is a bit like asking:
    Could you please give me a complete college education in an email thread?

    Here are some of the basic steps:
    - Create a test bench that stimulates the Verilog HDL or VHDL code correctly;
    - Functionally simulate the Verilog HDL or VHDL code until it works for you;
    - Synthesize the Verilog HDL or VHDL to gates (using any standard cell library);
    - Place those gates into a physical layout using any Place & Route tool;
    - Route between those gates using same Place & Route tool (e.g., SOC Encounter);
    - Handle power grid, signal intgegrity, timing, and area constraints;
    - Add design for manufacturing (e.g., scan chain, test points, etc.);
    - Add I/O pads & texted bond pads (pin-grid-array anyone?);
    - Physically verify design rules (DRC) & electrical correctness (LVS);
    - Parasitically extract & back annotate into your original netlist;
    - Functionally resimulate to your satisfaction (meeting specifications);
    - etc.

    Folks. Did I skip anything major?

    P.S. Whom do you work for? I have a stack of resumes from QUALIFIED people
    who can do that job above without asking the questions you ask.
  3. boki

    boki Guest

    I am a student, thank you very much.

  4. Guest

    Are you trying to cut corners for VLSI class? Then get over it and
    learn Verilog.

    Ok you need to tell us what software program you are using I must have
    missed that. Are you using Cadence for layout
    Perfect conversion is impossible.

    Some tools allow you to include VHDL code. Or the other way around did
    you use the help files?
    This might help you find the conversion tools however they are not
    perfect. to Verilog

    Or is it the layout that you have a problem with????
  5. boki

    boki Guest

    Yes, Cadence.
    Very useful reference, thank you very much.
    No, layout is ok, but never do Verilog to Layout before.

    Thank you very much.

  6. Guest

    everypost above bla

    Well it seem now I know why everyone is screaming at you I guess you
    wasted my time. Don't be scared of using help files that all great
    software comes with. I don't wish to argue over weather the help
    files are help full but sometimes they get you going in the right
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