how to choose the FPGA/DSP coprocessor system architecture

[[email protected]]

Dear All:

I am thinking about my system, the picture is here:

http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/

I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.

Two choices:

1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-

DPRAM

2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
DSP works as a coprocessor.
In choice 2, the USB could also connect from DSP but this will
accelerate processed data transfer, decelerate the raw data transfer.

Other questions:

I also need to store raw data, thus the data saving path will be
different:
Choice 1: the raw data will be from ADC -> DSP -> FLASH
Choice 2: the raw data will be from ADC -> FLASH -> DSP
It will meet the same question when I save processed data on board.

The last question is FIFO vs. DPRAM, FIFO could be implemented in
FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
flexibility for sure.

Thanks!

 

[David L. Jones]

Dear All:

I am thinking about my system, the picture is here:

http://www.flickr.com/photos/26914086@N05/3528643109/sizes/l/

I want to transfer the raw/processed image sensor data to USB 2.0 or
dpram.

Two choices:

1. ADC -> DSP, this means parallel ADC, then DSP processed data ->
USB, FPGA works as a coprocessor, use FPGA's DSP (difficult), FPGA-

2. ADC -> FPGA, this means serial ADC or whatever, then FPGA<----
EMIF---->DSP processed data, data feedbacked from DSP to FPGA -> USB,
DSP works as a coprocessor.
In choice 2, the USB could also connect from DSP but this will
accelerate processed data transfer, decelerate the raw data transfer.

Other questions:

I also need to store raw data, thus the data saving path will be
different:
Choice 1: the raw data will be from ADC -> DSP -> FLASH
Choice 2: the raw data will be from ADC -> FLASH -> DSP
It will meet the same question when I save processed data on board.

The last question is FIFO vs. DPRAM, FIFO could be implemented in
FPGA, could DPRAM be implemented in FPGA? the DPRAM has more
flexibility for sure.

Thanks!

It all hinges on what procesing speed you need.
Factors to consider are: how big is your image?, colour or B/W?, how many
frames per second?, and what sort of processing are you actually going?
DSP on it's own is by far the easist solution from a design and development
point of view. If the DSP is fast enough on its own then this is your best
option. Forget the FPGA co-processor unless absolutely necessary.
FPGA tools are in general difficult and troublesome, there are some easier
solutions around but they cost $$$$.
Why do you need to write the image data to FLASH? Do understand that FLASH
has a finite number of write cycles and is generally quite slow.
Tell us more about what the system actually needs to do.

Dave.

 

[[email protected]]

It all hinges on what procesing speed you need.
Factors to consider are: how big is your image?, colour or B/W?, how many
frames per second?, and what sort of processing are you actually going?
DSP on it's own is by far the easist solution from a design and development
point of view. If the DSP is fast enough on its own then this is your best
option. Forget the FPGA co-processor unless absolutely necessary.
FPGA tools are in general difficult and troublesome, there are some easier
solutions around but they cost $$$$.
Why do you need to write the image data to FLASH? Do understand that FLASH
has a finite number of write cycles and is generally quite slow.
Tell us more about what the system actually needs to do.

Dave.

linear ccd sensor (512/1024 points) for fast spetral scanning use,
like advanced astrophysics telescope. need DFT, filtering,
deconvolution, a lots of calculation. I also want to save raw data
every a couple of days. field use.