Connect with us

How to alternate 2 flip flops with 2 clocks?

Discussion in 'General Electronics Discussion' started by Johnyradio, Nov 11, 2012.

Scroll to continue with content
  1. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    Hello

    I've got two flip-flops, F1 and F2.
    And a clock C1. Every time the C1 goes High, it should drive F1 high and F2 low.
    There's a slower clock, C2. When C2 goes High, it should drive F2 high and F1 low.
    If C1 and C2 go high at the same time, C2 wins.

    How to do this?

    Thank You.
     
  2. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    From your description, it seems that F1 and F2 outputs are always the opposite of each other. Therefore you only need one flip-flop.

    I would use a SR flip-flop, and convert rising edges on CLK1 and CLK2 to very short pulses to set and reset the flip-flop. CLK2 can be given priority over CLK1 by generating a longer pulse from it.

    The whole thing can be done with a quad NAND gate. Here's a schematic. I'm afraid I couldn't simulate the exact version shown, which uses a 74HC132 or CD4093 quad NAND gate with Schmitt trigger inputs, but using a 74HC00 it seems to simulate OK.

    [​IMG]

    Edit: If rising edges on CLK1 and CLK2 occur at the same time, during the overlap between the two pulses, both outputs will be high simultaneously, instead of them being complementary (which they normally are). If this is a problem, use OUT2 and an inverted version of OUT2, and ignore OUT1.
     

    Attached Files:

    Last edited: Nov 12, 2012
  3. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    I appreciate that, but I'm slightly modifying my goal. This change, however, might not change your solution:

    I've got a SPDT switch, S1.
    And a clock C1. Every time the C1 goes High, it should drive S1 high (switch to position 1).
    There's a slower clock, C2. When C2 goes High, it should drive S1 low (switch to position 2).
    If C1 and C2 go high at the same time, C2 wins.

    I'm thinking the flip flip you described may drive the SPDT.
     
  4. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    I assume you mean an electrical switch such as a 4053. Yes, the output of the flip-flop can drive a CMOS bilateral switch device. There are other analogue switch devices available if you need special features (e.g. voltages outside the power supply rails); look on Digikey or Mouser.
     
  5. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    By electrical, I assume you mean solid state? No special needs, just low power, within the rails.
     
  6. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    Yes, I mean solid state. Check out the CD4053.
     
  7. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    Here's a simpler solution that was suggested to me.
    [​IMG]

    Here's my version of the same circuit. (note, the D's are not part of the solution, they are use to generate C2):
    [​IMG]

    It seems like a great idea. I prefer it's single-component simplicity to your solution (no offense).

    But as you can see from the trace (below), the output is not going high and low as desired. I need Q to go high on the first C1 rise after the first C2 rise, as described in the OP.

    another issue with this solution is, i'm seeing rises in the output on C1 falls, which is not desired. All changes should happen only on rising edges....

    [​IMG]

    I'd like to go with the simpler solution if possible. Any ideas?

    thank you!
     
    Last edited: Nov 13, 2012
  8. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    I think you need to rethink your requirements. Your definition of the behaviour you want is not clear. Your first post says "When C1 goes high" and "When C2 goes high" which to me implies edge-triggered behaviour. The 4013-based suggestion will give you edge-triggered behaviour (with a short delay) for C1, but not C2. The output will be HELD low WHILE C2 is high. Is that what you want?

    Your schematic is interesting. Your C2 clock is derived from your C1 clock using two cascaded T flip-flops, i.e. a divide-by-4 circuit. Is this just for testing, or is it your final design? If the two clocks are synchronous, there will be a much easier way to design the circuit.

    I had assumed the clocks were asynchronous, which was why you needed the edge-triggered behaviour. If that's not the case, your output can be defined in terms of a single clock input. Can you write up this definition? It should become clear that the logic you need is quite simple. Just describe the behaviour you want to see at "V3" (the output) in terms of the transitions at "V1" (the input).
     
  9. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    The correct description is my 2nd post. You can disregard my first post.

    The clocks ARE synchronous. The slower clock will always be a division of the source clock, but not necessarily divide-by-4. Could be 2, 4, 8, 12, 16, 24, etc.

    Thanks for requesting clarification.
     
  10. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    The description in your second post is not clear enough either.

    Can you give a general description of what you're trying to do with this circuit? Or is that information classified?

    Assume that the division will be by 4, and describe the sequence of signals you want on your output, in terms of the clock pulses on the input.
     
  11. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    Well... I have 2 analog signals coming in. I want to let only one of them pass at a time, hence the SPDT.

    The clocks are part of a process I can't disclose, and which doesn't have any bearing on this specific problem.

    When the slow clock goes high, the switch must pass the first analog input, no matter what the fast clock is doing (t so happens that the fast clock will always go high when the slow clock goes high, as you now know).

    But as soon as the fast clock goes high again, it switches the SPDT over to the 2nd analog input. The switch simply needs to remain in that position-- until the slow clock goes high again. So the intervening fast clock pulses could be safely ignored, if that would make things any easier.

    So, there are only two pulses we care about-- each slow-clock pulse, and then only the fast clock pulse immediately after it.
     
  12. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    Bzzzzt! You don't know how to do what you want; you've admitted that. But you're quite sure that explaining the purpose of your design "doesn't have any bearing" on solving your problem? I'm sure it would at least help me to understand what you're trying to do, and exactly what you need, since you are not clear on this yourself.

    You don't need to worry that you're inventing the next Big Thing and someone here will steal your idea and patent it if you disclose it. I actually think it's quite rude to ask for help but deliberately withhold information that might help us help you.

    If you were able to clearly define your requirements, it wouldn't be such an issue. But I think I've figured out what you want now.

    OK. So on the rising edge of the slow clock, the output is forced low (say), even if there is a rising edge on the slow clock at the same time. Otherwise, rising edges on the fast clock set the output high.

    This can be done easily with a D flip-flop (half a 4013). Tie the D input high, and feed the fast clock into the clock input. This takes care of the second part of your requirement. Then you need to convert rising edges on the slow clock into a short pulse that you can feed to the R input, to hold the flip-flop cleared (so it will ignore the clock pulse) during, and for a short time after, the rising edge on the slow clock. You can use a C-R differentiator for this:

    . . . . . . . . . . . . . . . 1k . . 100 pF
    Slow clock >----------\/\/\/\/-----| |------------------------> Reset input of flip-flop
    . . . . . . . . . . . . . . . . . . . . . . . . .|
    . . . . . . . . . . . . . . . . . . . . . . . . . ----\/\/\/\/-----0V
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10k

    Tie the Set input low.
     
  13. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    I appreciate your help. I do know what my goal is with that switch and the clocks.

    I havent diagrammed your solution yet, but it sounds like you're using a bit of rc delay to avoid conflict between the clocks, rather than logic.

    That concerns me for two reasons-- i cannot necessarily predict the ratio between the clocks, nor the speeds, so i worry that I'd have to tweak the rc values depending, and then my speeds would be constrained by the fixed rc values. And, I'm "philosophically" partial to a logic solution, rather than a filter solution.

    Am I misunderstanding your solution?

    Many thanks!
     
  14. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    You may KNOW your goal, but you also need to be able to communicate it in your posts.
    Yes. The same is true of my original suggestion and the earlier 4013-based suggestion that you posted.
    Right. This is an example of information you should have provided up-front. "What is the range of clock speeds he wants to use" is one of the questions I was asking myself as I read your posts.
    Even logic devices have timing requirements and specifications such as setup, hold, propagation delay etc. With a 4013 these are in the order of hundreds of nanoseconds, and everything gets faster with a higher supply voltage. Adding an external delay simply makes the circuit's timing requirements longer.

    Can you specify the timing relationship between the rising edges on the two clocks? For example, will it always be less than a microsecond either way? NO solution, whether it uses an explicit R-C delay or not, will work reliably, much less work perfectly, unless you can specify limits for values like timing offsets between the clocks, rise and fall times, minimum high and low periods, and maximum clock rates.

    For example if you can guarantee that the slow clock won't ever be faster than say 100 kHz and its high and low periods will always be say 2 us wide, there's no problem with adding an R-C circuit. You will need to recalculate the values though. The values I suggested are just approximate rule-of-thumb values.
     
  15. Johnyradio

    Johnyradio

    34
    0
    Oct 30, 2012
    My bad for failing to give more details up-front. I'm still learning-- but also, I was hoping (maybe naively) for a logic solution, and therefor assumed different rates would not require adjusting rc values. I'll state that the best solution would work with varying fast clock speeds, ranging from 500 kHz to 3 MHz.

    The slow clock will be fixed at 100 kHz.

    It's only the fast clock which may vary. It's highest speed would be about 3 MHz.
     
  16. KrisBlueNZ

    KrisBlueNZ Sadly passed away in 2015

    8,393
    1,271
    Nov 28, 2011
    Different clock rates will not require adjusting RC values. You just need to ensure that the pulse generated from the slow clock (by the C-R differentiator) is comfortably shorter than the minimum interval between fast clock pulses. If the fast clock is slower than that, the circuit will still work fine.

    I hadn't guessed you were operating at such a high frequency. My ESP isn't as good as it once was. And that is a significant factor in the design decisions. The CD4013 is specified higher than 3 MHz but I would use a 74HC74 instead. Do you have a 5V supply rail?

    If you want to guarantee correct and glitch-free operation of ANY solution, you need to specify the parameters I listed in my previous post. You've given the frequency ranges for both clocks; now you need to specify the minimum high and low periods for each clock, maximum rise and fall times for the clocks, and most importantly the maximum timing offset between rising edges on the different clocks.

    Will the slow clock be derived from the fast clock using a circuit that's under your control? If so, that circuit will have a maximum propagation delay. Can you calculate that delay?
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-