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How to acquire an accurate delay time?

Discussion in 'Electronic Design' started by Fox zhou, Oct 21, 2004.

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  1. Fox zhou

    Fox zhou Guest

    I'd like to acquire a programmable delay time (10-50us, under 1ns
    accuracy) after a trigger signal. How could I do?

    Here is my proposed way: I use a low jitter and accurate clock (eg:
    100MHz) and a counter to create the rough delay time and use the delay
    line or some other chips to generate the fine delay time. When both of
    them are added together, the expected delay time is acquired.

    My questions are:

    1. What kind of clock generator should I use? I hope that is a
    single chip solution with the 100MHz with 10ps RMS jitter.
    2. How to synchronize with the trigger signal? The idea situation is
    that the trigger edge is same overlap with the counter driver's edge
    (the rising of falling edge of the clock). But the trigger signal is
    un-controllable. It may arrive at any point of the cycle. That is to
    say the max error is a cycle time (10ns). That is not acceptable.
    3. Are there any other ways to complete my case?

    Any of your suggestions and new ideas is welcome.
  2. Any synchroneous delay is synchroneous to the clock and in your case
    this leaves an uncertainity of 5ns average and 10ns worst case.

    For a synchroneous solution you'd need a clock of shorter than 1ns,
    meaning more than 1GHz. There however a synchroneous counter of
    16 bits (for 50000 counts) are definitely an achievement.

  3. Mac

    Mac Guest

    You can combine analog and digital techniques to do better. I posted a
    sketch of my idea concerning this elsewhere in the thread.

  4. Mac

    Mac Guest

    I think you are on the right track.

    We have a piece of lab equipment at work (made by stanford research, I
    think) which generates delays with very high resolution.

    The way it works is that all logic is converted to ECL internally, and it
    measures the time from the trigger to the first clock rising edge by
    discharging (or charging, I can't remember) a capacitor.

    When the clock rising edge is detected, the capacitor charge or discharge
    stops, and the digital counter starts. When the digital counter is done,
    the capacitor continues its charge or discharge until it reaches
    a programmable threshold, then the output trigger fires.

    I may have some details wrong, but the basic idea is that when you take
    your desired delay, you can subtract out the full clock cycles, and you
    have a certain amount of analog delay left. This analog delay corresponds
    pretty precisely to a certain amount of charge on a capacitor. You allow
    some of this to be spent after the input trigger and before the first
    rising edge of the clock, and the balance is spent after the last whole
    clock. This gives you a very precise, very low jitter delay.

    All of digital logic is synchronized to the ultra-low jitter clock with
    ECL flip-flops.

    I know all this because the piece of equipment comes with a complete
    schematic and a detailed explanation of the theory behind it. I still
    didn't fully get it, but it was pretty cool.

    The schematic, by the way, was completely hand-drawn.

  5. Robert Baer

    Robert Baer Guest

    There is a way to guarantee timing delay from trigger and still use a
    The trigger turns on a gated oscillator, which might be the "coarse"
    timing delay (say 100MHz for 10nSec steps).
    I have seen this done with an ECL gate, and the first half-cycle at
    its output was the only reduced amplitude waveform in the output
    Finer steps easily obtained by selecting a tap in a delay line.
  6. Analogue Devices sell fixed delay lines with taps - use an FPGA to select
    which tap to derive the delay from for the short delays and count several
    periods for long delays. An algorithm in a microprocessor can choose the
    best combination. Very precise, very flexible and cheap too.

    I used that for a Radar once.
  7. Fox zhou

    Fox zhou Guest

    Thank you Mac. Where can I find your sketch. I am the green hand in this group. ;-)

  8. Fox zhou

    Fox zhou Guest

    I think it's a good way to use the clock Rene. But we could not
    gurrantee the synchronization of the clock's edge and the trigger's
    dege. There are the error between the "coarse" timing delay and the
    delay what we are expected(shown as below). The maxium error is the
    10ns. That is terroble.

    Trigger | T |
    CLK ______-----_____-----_____
  9. Fox zhou

    Fox zhou Guest

    Thank you Mac. I am trying this method. My way is to use the trigger's
    edge to turn on a switch then the constant current source can charge
    the capacitor. When the first edge of the clock arrives, it turns off
    the switch. Therefore, the voltage of the capacitor is proportionate
    with the missing time. (That is called Time-to-Amplitude)If I use a
    ADC to digitalize the this voltage, I can get the missing time data.
    Using the delay line, I think, this missing time can be compensated.

    I think my way is similar to the algorithm of your instrument. My
    current problem is how to realize the switch circuit. It should be an
    analog switch with high switch speed.

    I'd like to know your equipment handles this case.

  10. Fox zhou wrote:

    The switch can be a FET or a bipolar, I guess.

  11. Yes, the SRS535, if I remember correctly.
    The used AD9501 digital delay generators are out of sale now.

  12. John Larkin

    John Larkin Guest

    The ways I know of are...

    1. The HP technique: run an ECL delay-line oscillator. When the
    trigger is received, stop it briefly and restart it, use the resulting
    clock to time counts, and use an analog ramp vernier for the fine
    delay. Whenever the oscillator is running, it's phase-locked to a
    crystal oscillator using a heterodyne technique that doesn't (much)
    quantize the phase of the oscillator to the crystal. Fairly complex.
    Copied by LeCroy and Berkeley Nucleonics. Patented by Chen in the

    2. Jitter correction, a la SRS535: run the trigger edge through a
    dual-rank synchronizer, clocked from a crystal oscillator, resulting
    in a pulse from 1 to 2 clocks wide. Use a ramp to convert this to a
    voltage Vj. Now do a digital delay (just count xtal clocks) and an
    analog ramp vernier, but add Vj into the vernier control voltage to
    compensate the jitter.

    3. Pepper's technique: Make a regular single-slope ramp (triggered
    ramp, dac, comparator) analog delay generator that covers some range,
    say 0-50 ns. For longer delays, cut off the current source for N
    clocks of, say, a 100 MHz oscillator, suspending the ramp as needed.
    This is wonderful, except for some practical leakage issues. Patented
    by Pepper around 1990, I think.

    4. My technique: at trigger time, start an LC oscillator, 50 MHz
    maybe, and use it to time the digital part of the delay, then make up
    the last 20 ns with an analog ramp vernier delay. Have a flash ADC,
    clocked by a crystal osc, digitize the waveform coming out of the LC
    osc, observe it long enough to quantify the phase of the LC relative
    to the xtal, and close a DSP feedback loop on the LC osc, with a
    varicap, to lock the relative frequency and phase of the LC to the

    5. Ditto. Start a coaxial ceramic resonator oscillator, 600 MHz maybe,
    at trigger time, and use it to time delays. It's not as accurate as a
    crystal oscillator, but pretty good for shortish delays.

    6. Start a crystal oscillator at trigger time, and use it to time
    counts, followed by an analog vernier delay. HP did this in at least
    one instrument, but it's very nasty. Crystals don't like to be started
    or stopped very quick.

    None of these are easy.

    My stuff is at Signal Recovery makes the
    Pepper instrument these days. SRS makes the 535. Neither of the
    mentioned HP delay generators are still in production.

  13. mike

    mike Guest

    There's a thing called a "gated restart oscillator".
    You let it freerun and pll it to a reference. The trigger
    stops/restarts the oscillator in a known phase relationship
    to the trigger. The "out-of-phaseness" in the pll is your
    measurement...once you subtract out the stop time.

    Return address is VALID.
    500MHz Tek DSOscilloscope TDS540
    Wanted, 12.1" LCD for Gateway Solo 5300. Samsung LT121SU-121
    Bunch of stuff For Sale and Wanted at the link below.
  14. Fox zhou

    Fox zhou Guest

  15. Fox zhou

    Fox zhou Guest

    Analogue Devices sell fixed delay lines with taps - use an FPGA to select
    I guess what you said is the AD9501. Could you tell me more details
    about it? I have tested the DALLAS's DS1020. That is a wonderful delay
    line chip. Which one is more suitable to my case.

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