How do I calculate this?

[Larry Brasfield]

If an AMD processor with no special power-saving features is drawing 200 Watts
while running at 2 GHz with a 200Mhz Front side buss, How many watts will it
draw while running at 1 GHz with a 100Mhz FFB? 100W? Is that the formula,
half the frequency means half the heat generated?

That is very close for CMOS logic, such as
comprises most of modern microprocessors.

Or is it more complicated than that?

Not enough so to worry about.

 

[Paul Keinanen]

That is very close for CMOS logic, such as
comprises most of modern microprocessors.


Not enough so to worry about.

Except that at 1 GHz, the processor would be able to run at a lower
core voltage. The power dissipation is proportional to the core
voltage squared.

Paul

 

[I.Hope.The. [email protected]]

If an AMD processor with no special power-saving features is drawing 200 Watts
while running at 2 GHz with a 200Mhz Front side buss, How many watts will it
draw while running at 1 GHz with a 100Mhz FFB? 100W? Is that the formula,
half the frequency means half the heat generated? Or is it more complicated
than that?

 

[Larry Brasfield]

Except that at 1 GHz, the processor would be able to run at a lower
core voltage. The power dissipation is proportional to the core
voltage squared.

The OP strongly implied that unmentioned variables
were unchanged. His question makes little sense
otherwise. If we must mention all those variables,
we should include loading on the uP pins, nature
of the code being run, its time dependencies, etc.

 

[Genome]

Except that at 1 GHz, the processor would be able to run at a lower
core voltage. The power dissipation is proportional to the core
voltage squared.

Paul

Do they do that?

I know that some microprocessor power supply contollers are supplied with
D/A converters to adjust the output voltage.

Sort of makes sense that they might be able to do it dynamically according
to the sums being done.

Clever stuff.

DNA

 

[Keith Williams]

That is very close for CMOS logic, such as
comprises most of modern microprocessors.

The processes that modern microprocessors use leak like hell (both gate
oxide tunneling and sub-threshold) and it's getting worse. Much of the
power dissipation is DC and is unaffected by the clock frequency. Only
the dynamic power component is proportional to frequency.

Not enough so to worry about.

Complete bullshit.

 

[Hans-Bernhard Broeker]

Do they do that?

Sure. For the range of processors being talked about here, whenever
power consumption of CPUs is seriously considered (e.g. because it's a
mobile computer running off a battery whose weight you have to
justify), core voltage modulation is a routine operation in modern
designs --- the capability of doing this dynamically is the only real
difference between e.g. Mobile and Desktop versions of the same x86
processor family. For the AMD processors mentioned by the OP, google
up "PowerNow!".

 

[Keith Williams]

Sure. For the range of processors being talked about here, whenever
power consumption of CPUs is seriously considered (e.g. because it's a
mobile computer running off a battery whose weight you have to
justify), core voltage modulation is a routine operation in modern
designs --- the capability of doing this dynamically is the only real
difference between e.g. Mobile and Desktop versions of the same x86
processor family. For the AMD processors mentioned by the OP, google
up "PowerNow!".

You're going to see more and more voltage and frequency modulation to
contain the power dissipation within the cooling solution (contain
magic smoke) and to reduce idle/sleep-mode power. Leakage is is a big
deal (worse than V^2), so reducing the idle voltage helps a *lot*.

 

[Genome]

Sure. For the range of processors being talked about here, whenever
power consumption of CPUs is seriously considered (e.g. because it's a
mobile computer running off a battery whose weight you have to
justify), core voltage modulation is a routine operation in modern
designs --- the capability of doing this dynamically is the only real
difference between e.g. Mobile and Desktop versions of the same x86
processor family. For the AMD processors mentioned by the OP, google
up "PowerNow!".

I have googled and I'll give you.

http://www.amd.com/us-en/assets/content_type/DownloadableAssets/Power_Now2.p
df

Which doesn't tell much.

And I'll raise you.

http://www.irf.com/product-info/datasheets/data/ir3080.pdf

Which has the DAC in it.

I'd have to guess that there is something in the 'software' that recognises
when it's time to 'Pump Up The Jam' and tells the power supply too 'Get
Juicy'.

DNA

 

[Eric]

Dynamic average power = Ctotal*Vdd^2*fclk

so assuming all 200W is dynamic power(which it is not)
Ctotal is constant
Vdd^2 is constant

Pavg is proportunal to fclk.

 

[Paul Keinanen]

If an AMD processor with no special power-saving features is drawing 200 Watts
while running at 2 GHz with a 200Mhz Front side buss, How many watts will it
draw while running at 1 GHz with a 100Mhz FFB? 100W? Is that the formula,
half the frequency means half the heat generated? Or is it more complicated
than that?

One other thing that is relevant mainly in real-time control systems.

In such systems, it is quite common to perform a more os less constant
amount of work (say 500000 instructions or cycles) at very regular
intervals (say every millisecond) and the rest of the interval, the
processor is idle. In this example, those 500000 cycles would take
0.25 ms in every interval to execute at 2 GHz.

Dropping the clock frequency to 1 GHz, it would now take 0.5 ms to
execute the program in each 1 ms interval. Although the instantaneous
power dissipation drops to 1/2, the execution time doubles, so the
total energy dissipated remains constant during each interval and
hence the average power dissipation remains constant.

The only gains that you can get some power saving in such applications
is from such circuits that are running constantly regardless if the
CPU is doing any real work or not or by lowering the core voltage.

Other systems that needs to do a constant amount of work
(instructions) in a specified time (such as various media players) may
behave in a similar manner.

Paul

 

[Larry Brasfield]

The processes that modern microprocessors use leak like hell (both gate
oxide tunneling and sub-threshold) and it's getting worse. Much of the
power dissipation is DC and is unaffected by the clock frequency.

Given that as a fact, one has to wonder why so much
trouble is taken with clock speed reduction in mobile
processors.

Only the dynamic power component is proportional to frequency.

True by definition and not at issue.

Complete bullshit.

Since you are so all-knowing, how about listing the DC
current versus dynamic current for a few AMD processors
to give the OP an idea of what kind of error he can expect
to incur by using the Idc == 0 approximation? (In other
words: "Evidence please.")

 

[Keith Williams]

Given that as a fact, one has to wonder why so much
trouble is taken with clock speed reduction in mobile
processors.

Reduce the clock speed and you can also reduce the voltage. Reduce the
voltage and the leakage decreases too (by at least the third power).
It's not hard to see why one reduces the clock speed in mobile
applications.

True by definition and not at issue.

No, not by definition. The dynamic power is also a second order
function of the voltage, is that the definition of "dynamic power"?
It *is* the issue, since the question was asked about (total) power,
not a component of the power.

Since you are so all-knowing, how about listing the DC
current versus dynamic current for a few AMD processors
to give the OP an idea of what kind of error he can expect
to incur by using the Idc == 0 approximation? (In other
words: "Evidence please.")

At 90nm and fast-sort processors, it's upwards of a 50% error (assuming
no Vcore modulation). Is that enough of an error to admit you haven't
been paying attention for a few years?

 

[Keith Williams]

One other thing that is relevant mainly in real-time control systems.

In such systems, it is quite common to perform a more os less constant
amount of work (say 500000 instructions or cycles) at very regular
intervals (say every millisecond) and the rest of the interval, the
processor is idle. In this example, those 500000 cycles would take
0.25 ms in every interval to execute at 2 GHz.

Dropping the clock frequency to 1 GHz, it would now take 0.5 ms to
execute the program in each 1 ms interval. Although the instantaneous
power dissipation drops to 1/2, the execution time doubles, so the
total energy dissipated remains constant during each interval and
hence the average power dissipation remains constant.

Yes, that's a very relevant observation. It's actually worse since
doubling the clock doesn't get twice as much work done (still the same
wait for memory, for instance). Also the Vcore can be throttled down
at a lower clock frequency, saving both dynamic and static power. If
the actual needs are known ahead of time, a processor intended for a
slower clock can save even more because it can be
designed/processed/sorted (in any combination) for low power rather
than high clock rates.

The only gains that you can get some power saving in such applications
is from such circuits that are running constantly regardless if the
CPU is doing any real work or not or by lowering the core voltage.

Sure, but if you lower both the voltage and the clock rate you may be
able to save even more.

Other systems that needs to do a constant amount of work
(instructions) in a specified time (such as various media players) may
behave in a similar manner.

Sure. In this case a processor chosen specifically for the application
is the best bet.

 

[John Larkin]

I'd have to guess that there is something in the 'software' that recognises
when it's time to 'Pump Up The Jam' and tells the power supply too 'Get
Juicy'.

DNA

As some very wise person [1] once noted, the best things in life are
sticky.

John

[1] it was me, actually.

 

[Endoscope]

I'd have to guess that there is something in the 'software' that recognises
when it's time to 'Pump Up The Jam' and tells the power supply too 'Get
Juicy'.

DNA

As some very wise person [1] once noted, the best things in life are
sticky.

John

[1] it was me, actually.

Yadda yadda yadda.


Go beat your chocolate.

DNA

 

[Larry Brasfield]

Reduce the clock speed and you can also reduce the voltage. Reduce the
voltage and the leakage decreases too (by at least the third power).
It's not hard to see why one reduces the clock speed in mobile
applications.
Interesting.


No, not by definition. The dynamic power is also a second order
function of the voltage, is that the definition of "dynamic power"?

Dynamic power is the power dissipated due to
charging capacitances. There was no voltage
change in the OP's question. Maybe that should
be assumed on his behalf.

It *is* the issue, since the question was asked about (total) power,
not a component of the power.

The question was how power varies when the clock
speed is changed.

At 90nm and fast-sort processors, it's upwards of a 50% error (assuming
no Vcore modulation). Is that enough of an error to admit you haven't
been paying attention for a few years?

Yes. The last time I looked into this, the short
channel and gate tunnelling effects were still on
the horizon as a predicted limit to Moore's law.

It looks like the OP needs to look at a spec for
the actual AMD part he has in mind.

 

[keith]

Dynamic power is the power dissipated due to
charging capacitances. There was no voltage
change in the OP's question. Maybe that should
be assumed on his behalf.


The question was how power varies when the clock
speed is changed.


Yes. The last time I looked into this, the short
channel and gate tunnelling effects were still on
the horizon as a predicted limit to Moore's law.

Will you never have a high enough IQ to be able to rent a clue? What,
pray tell, do you think the buzz has been about for the last couple of
years? Moore's law has come to a *big* speed-bump, and that's *LEAKAGE*.
Sheesh!

It looks like the OP needs to look at a spec for
the actual AMD part he has in mind.

IFF they want you to know the answer. If you're good (you're not) you
might be able to ferret out some information. However, they're (AMD and
Intel) cozy with the facts.

 

[Paul Keinanen]

The question was how power varies when the clock
speed is changed.

This is not a Trivial Pursuit game with a single correct answer or a
homework help desk for lazy students, this is a news group that
traditionally has been used for open ended discussions, in which
participants can learn from by actively taking part in the discussion
or by just following the discussion.

As in engineering in general, there are usually not a single "correct"
answer, but it usually depends on many factors, which were not obvious
or stated in the original posting that stated a thread.

If this was a homework, I hope that the original poster has been
followed the whole thread and learned much more than from just a
Yes/No answer.

Paul

 

[Larry Brasfield]

On Thu, 21 Apr 2005 18:02:36 -0700, "Larry Brasfield"

The following '|>>|' quoted text is restored context
necessary to understand Paul's bare quotation.

|>>|>> > Only the dynamic power component is proportional to frequency.
|>>|>>
|>>|>> True by definition and not at issue.
|>>|>
|>>|> No, not by definition. The dynamic power is also a second order
|>>|> function of the voltage, is that the definition of "dynamic power"?
|>>|
|>>|Dynamic power is the power dissipated due to
|>>|charging capacitances. There was no voltage
|>>|change in the OP's question. Maybe that should
|>>|be assumed on his behalf.
|>>|
|>>|> It *is* the issue, since the question was asked about (total) power,
|>>|> not a component of the power.
|>>|

This is not a Trivial Pursuit game with a single correct answer or a
homework help desk for lazy students, this is a news group that
traditionally has been used for open ended discussions, in which
participants can learn from by actively taking part in the discussion
or by just following the discussion.

I agree with what you are saying but object to your
use of a quote lifted out of its context to imply that I
need such a tutorial. Without the context, you make
it appear that I attempted to constrain the discussion.
The (now restored) context shows otherwise.

As in engineering in general, there are usually not a single "correct"
answer, but it usually depends on many factors, which were not obvious
or stated in the original posting that stated a thread.

That lesson, too, is worthy but already well taken.
....