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Help with circuit (voltage doubler)

Discussion in 'General Electronics Discussion' started by vjtgru, Aug 31, 2016.

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  1. vjtgru


    Aug 31, 2016
    I need some help with the following circuit: [​IMG]
    I simulate it using LTSpice IV and have this:
    But I couldn't get that thinking. Of course, I know that it's possible that there's some DC voltage before the capacitor C2 if it's Ground on the other side, but I couldn't get that.

    For example, I thought that, in Vnode, it had to be something like the characteristic curve of a capacitor discharging in a AC voltage.

    Any help will be appreciated. Thanks!
  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    The even simpler way to describe it is to imagine all caps are discharged.

    Then consider the case on Vin being negative wrt ground. C1 is charged to -Vin (the negative end is at the point labelled Vin)

    Now, when the point Vin is +ve, this voltage is added to that on C1 is seen by C2. After a few cycles, C2 will be charged to 2*Vin.
  3. Colin Mitchell

    Colin Mitchell

    Aug 31, 2014
    Starting at the first half cycle. Nothing happens when the input goes positive.
    But when it goes negative, diode D2 flips over an the cathode goes below the lower rail and it prevents the right lead of C1 going any lower than minus 0.7v.
    The left lead of C1 goes lower than the bottom rail by an amount equal to the incoming voltage.
    This means C1 becomes charged and it is not charged in the normal way we think about charging a capacitor by charging the positive terminal of the capacitor.
    It is charged by charging the negative terminal.
    But this does not matter as the capacitor is now charged and it has say 10v or 50v across it.
    When the input signal starts to rise from its level of say minus 10v or 50v, the capacitor starts to rise and the negative lead is pushed up, making the positive lead rise too.
    When the input voltage is plus 50v, the capacitor is sitting on top of this voltage and the positive lead of the capacitor is at 100v.
    This voltage can now pass through D1 to the output and charge the second capacitor.
    Without getting too technical, the second capacitor cannot charge to 100v because the first capacitor will be delivering its energy and its voltage will fall. The end result will be about 75v.
    This is important because, on the next cycle, the capacitor will only be “topped up” as it will still have some energy inside it.
    As the incoming waveform drops, the right lead of the first capacitor will fall and it will no-longer be able to deliver its energy to the second capacitor.
    To prevent the second capacitor delivering its energy to the first capacitor we have D1.
    The input voltage drops, the first capacitor flips over and when the input voltage is low enough, the first capacitor gets topped up to continue the charging cycle.
    Eventually the second capacitor gets to nearly 100v.
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