Yes, I've got the bits but the resonators' part number is not-known.
I imagine they're probably Murata; in any event they're the two-
terminal, dipped type. As for the diodes, Frank's design calls for
BB914s, but I couldn't source them so am using BB149 as they have
the largest ratios I could source here. I also have some BBY40s
which are higher capacitance and lower V/C ratio.
Further info: the output is to be fed into a 5X multiplier to get
into the 40Mhz band. The varactors have to sweep the (final) output
between (preferably) 40.5 and 41Mhz; or if not, 40.6 and 41Mhz would
probably suffice...
I can get quartz crystals made up for the exact frequency for the
midband (40.750/5=8.15Mhz) but they won't pull much; nence the need
for a nice "rubbery" ceramic resonator.
Okay, Paul, try this:
varactor *buffered*
BBY40 100pF inverter
6 to 45pF || |\
+--->|---+---||---+-----| >O----+--- output
| | || | |/ |
GND .-. | ___ |
| | +----|___|----+
| | 10M | 10M |
'-' | .-.
| | ceramic | |
DC control --+ | resonator | | 100k
0-15V | | _ '-'
--- | | | |
--- u10 +----|| ||----+
| |_| |
GND ---
8MHz --- 100pF
|
GND
The capacitance shown for the BBY40 is the typical range taken from
the data sheet curves (.8V to 15V). I am suggesting you use a normal,
*buffered* gate in order to keep the ac signal on the input of the
gate from modulating the control voltage on the varactor. As I
recall, a buffered gate should have a gain of around 60dB or more
(1000x) in the linear mode. Unfortunately, gain can vary with all
sorts of things, temperature, operating voltage and even manufacturer.
The 100k resistor coming from the output of the gate forms a voltage
divider with the 100pF capacitor it feeds. It serves both to provide
phase shift and control loop gain. Be prepared to lower its value if
the circuit does not start or raise its value if the oscillations are
not clean or lock onto spurious modes (my guess as to gate gain is
just that - only a guess).
According to Murata the 10M dc biasing resistor across the gate may
not be needed because the leakage across the resonator is usually
sufficient for that purpose. Whatever you do, just be sure not to
go below about 4.7M for either the gate bias or the control bias
resistors as doing so erodes oscillator Q and narrows the control
range. Control range, by the way, should be 1.5 to 2 times greater
than you were asking for (~900kHz referred to 40MHz).
Here is the LTspice simulation file for your circuit.
(As usual, beware inadvertent line wrap.)
____________Ceramic_Resonator.asc______________
Version 4
SHEET 1 1588 680
WIRE 576 256 608 256
WIRE 720 256 736 256
WIRE 288 256 320 256
WIRE 176 112 320 112
WIRE 768 112 768 256
WIRE 608 336 608 368
WIRE 368 256 352 256
WIRE 464 256 448 256
WIRE 496 256 464 256
WIRE 608 272 608 256
WIRE 608 256 640 256
WIRE 768 448 768 480
WIRE 768 384 768 368
WIRE 768 272 768 256
WIRE 176 256 176 112
WIRE 208 256 192 256
WIRE 768 368 816 368
WIRE 768 368 768 336
WIRE 976 368 976 384
WIRE 976 464 976 480
WIRE 928 368 960 368
WIRE 640 256 656 256
WIRE 736 256 768 256
WIRE 816 368 848 368
WIRE 960 368 976 368
WIRE 320 144 320 112
WIRE 320 112 768 112
WIRE 320 256 320 224
WIRE 320 256 352 256
WIRE 192 256 176 256
FLAG 608 368 0
FLAG 352 256 1
FLAG 464 256 2
FLAG 640 256 3
FLAG 768 480 0
FLAG 976 480 0
FLAG 736 256 4
FLAG 816 368 5
FLAG 960 368 6
FLAG 192 256 4
SYMBOL Misc\\xtal 720 240 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 Invisible 0
SYMATTR InstName Y1
SYMATTR Value 6p
SYMATTR SpiceLine Rser=7 Lser=74u Rpar=1e8 Cpar=33p
SYMBOL cap 592 272 R0
WINDOW 0 40 24 Left 0
WINDOW 3 40 47 Left 0
SYMATTR InstName C1
SYMATTR Value 100p
SYMBOL voltage 352 256 R270
WINDOW 0 32 56 VTop 0
WINDOW 3 -60 56 VBottom 0
WINDOW 123 -32 56 VBottom 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value ""
SYMATTR Value2 AC 1
SYMBOL res 592 240 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R1
SYMATTR Value 100k
SYMBOL varactor 752 448 M180
WINDOW 0 40 32 Left 0
WINDOW 3 40 9 Left 0
SYMATTR InstName D1
SYMATTR Value {C}
SYMATTR Prefix C
SYMATTR SpiceLine Rser=5
SYMBOL cap 752 272 R0
WINDOW 0 40 24 Left 0
WINDOW 3 40 48 Left 0
SYMATTR InstName C2
SYMATTR Value 100p
SYMBOL Misc\\EuropeanResistor 192 272 R270
WINDOW 0 27 56 VTop 0
WINDOW 3 5 56 VBottom 0
SYMATTR InstName U1
SYMATTR Value Gate
SYMATTR Prefix X
SYMBOL voltage 976 368 R0
WINDOW 0 40 48 Left 0
WINDOW 3 41 72 Left 0
SYMATTR InstName V2
SYMATTR Value 2.52
SYMBOL res 944 352 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R2
SYMATTR Value 10Meg
SYMBOL res 336 240 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R3
SYMATTR Value 10Meg
TEXT 168 16 Left 0 !.step param C list 6p 45p
TEXT 168 48 Left 0 !.tran 0 .3m 0 .1u uic
TEXT 168 -16 Left 0 !.param C=31p
TEXT 176 336 Left 0 !.SubCkt Gate 1 2\nV1 3 0 2.5V\nG1 2 0 1 3 100\nD1 0 2 clamp\n.model clamp D( Ron=0 Roff=10 Vfwd=0 Vrev=5)\n.ends
TEXT 960 336 Bottom 0 ;Control\nVoltage\n0-15V
TEXT 792 464 Left 0 ;BBY40
TEXT 168 80 Left 0 !.ac lin 1000 7e6 9e6
TEXT 520 -8 Left 0 ;for Loop Gain\n(ac analysis)\nplot V(1)/V(2)