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help for VHDL and DAC

Discussion in 'Electronic Design' started by [email protected], Oct 13, 2005.

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  1. Guest

    Hi, I am designing a VCO at 24GHz (RF stuff) for my master thesis. I
    am working now on the control circuit which outputs a series of data to
    control the oscillator. I have already this table, and I am trying to
    implement it in FPGA. As I am new with this , I still cannot figure out
    how to write out a series of data in certain clock rate. I am using the
    ISE7.1 from Xilinx and the FPGA is XC2S200E on a D2E board from
    Digilent. Can anybody give me a hint, or suggest some literature?
    Another thing is: I will use a DA converter to convert the output
    signal from FPGA to analog format. Therefore after the DA converter
    which I will buy, I need to design a filter to smooth the signal
    (between two points, it should be something like linear). The output
    signal from the DA converter should have a signal rate of 50kHz, how
    should I specify the filter. ps: the filter will be connected to the
    control port whose input impedance is capacitive. Any suggestions will
    be welcome.
    Many thanks
    Brandon Xin
  2. PeteS

    PeteS Guest

    Taking the questions one at a time
    Are the output data to be shifted out serially or parallel?

    If serially, implement a shift register and assign one end or the other
    (depending on whether you want msb or lsb first) to an output pin. You
    then have to clock it at the data rate and make sure you have valid
    data in there (I suggest looking at UART implementations for clues on
    how to do this as doing it yourself will be better than us telling

    If parallel, then clock your data into an internal shift register, and
    then assign that data in a parallel fashion to n output pins (where n
    is the number of bits in the sample).

    Are the data you are converting originally from an analogue source? If
    so, and they were encoded in the normal manner, you will need a raised
    cosine filter after the DAC to eliminate SinX/X distortion (inherent in
    the coding process).

    I assume you are talking about a *sample rate* of 50kHz - is that
    50kbit/sec or 50 kSamples (bits x n) per sec?

    In either case (assuming the data represent an analogue signal that was
    normally coded), the output filter should cutoff at less than half the
    **sample** rate (not the bit rate - This is the Nyquist limit).


  3. How big is the table? If it's small (and you're using Xilinx
    parts) you can set the data up in a SRL16[*] (or a few) and shift
    it. If it's larger you could implement a ROM and increment an
    address counter to access the data.

    [*] The SRL16 is a slick LUT option that configures a single LUT
    as a 16bit synchronous FIFO; *very* useful for delay queues and

  4. You have a GUNN and try to lock it to a frequency proportional to a DAC
    output ? You want to FM modulate a GUNN ?

  5. Guest

    Hi, thanks Pete:
    I will gerenate a stream of data from the FPGA, so it will be
    parallel output. The clock rate will be 50kHz, that means it is
    50kSamples/sec. But how can I set the data into the Series Register?
    How do I do in ISE7.1? What do you mean with UART?
    About the filter, the problem is the following: I have a step
    function from the output of the DA converter, each step has a duration
    of (1/50k)s. But I want to smooth this signal, so I should implement a
    low pass filter, I would think the cut off frequency would be 50kHz, or
    no? I don't think this has anything to do with the Nyquist limit.
    Brandon Xin
  6. Rich Grise

    Rich Grise Guest

    Um, draw a line from the data source to the input of the shift register?
    That would be in "schematic" mode, of course. ISE comes with about two
    dozen example circuits, and great tutorials (although you might have to
    download the tutorials).
    Typically, Universal Asynchronous Receiver-Transmitter.
    It kind of sounds like you need to go and reread your text books.

    Good Luck!
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