help: capture generates netlist to allegro

[Newer]

After I DRCed my schematics without errors, I began to creat netlist
to allegro, but it always reported the following error info , so that
,i cann't get the netlist properly. I want to know the reason,please
help me . Thanks a lot


********************************************************************************
*
* Netlisting the design
*
********************************************************************************
Design Name:
D:\CADENCE\WORKSPACE\Orcad_SGWH\sgw_h.dsn
Netlist Directory:
D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO
Configuration File:
D:\Cadence\PSD_15.0\tools\capture\allegro.cfg

Spawning... "D:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d
"D:\CADENCE\WORKSPACE\Orcad_SGWH\sgw_h.dsn" -n
"D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO" -c
"D:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "PCB
Footprint"
#1 Warning [ALG0047] "No_connect" property on Pin "PR3.9" ignored for
PR3: SCHEMATIC1, SGW_H4 (12.10, 3.60). Connecting pin to net "A23".
#2 Warning [ALG0016] Part Name "CONN JACK PWR_TH3PIN_CONN JACK PWR" is
renamed to "CONN JACK PWR_TH3PIN_CONN JACK".
#3 Warning [ALG0016] Part Name "LM2576T3P3_TO220PINS5_LM2576T3P3" is
renamed to "LM2576T3P3_TO220PINS5_LM2576T3P".
#4 Warning [ALG0016] Part Name
"MT48LC16M16A2_TSOPII54PIN_MT48LC16M16A2" is renamed to
"MT48LC16M16A2_TSOPII54PIN_MT48L".
Scanning netlist files ...
Loading... D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO/pstchip.dat
Loading... D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO/pstchip.dat
Loading... D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO/pstxprt.dat
#38 DDB_ERROR: Terminating character ':' not found on line 11.
DDB_INFO: File
D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO/pstxprt.dat not loaded.
Error: Line 11 in file
D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO/pstxprt.dat:
Error loading the parts list file
Detected in function: ddbLoadPstX
Files
#5 Error [ALG0036] Unable to read logical netlist data.

Exiting... "D:\Cadence\PSD_15.0\tools\capture\pstswp.exe" -pst -d
"D:\CADENCE\WORKSPACE\Orcad_SGWH\sgw_h.dsn" -n
"D:\CADENCE\WORKSPACE\ORCAD_SGWH\ALLEGRO" -c
"D:\Cadence\PSD_15.0\tools\capture\allegro.cfg" -v 3 -j "PCB
Footprint"


*** Done ***

 

[Boris Mohar]

After I DRCed my schematics without errors, I began to creat netlist
to allegro, but it always reported the following error info , so that
,i cann't get the netlist properly. I want to know the reason,please
help me . Thanks a lot

I don't use Allegro but your foot long part names might be a problem.



Regards,

Boris Mohar

Got Knock? - see:
Viatrack Printed Circuit Designs http://www3.sympatico.ca/borism/