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HCT4051 leakage

Discussion in 'Electronic Design' started by John Larkin, Nov 30, 2005.

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  1. John Larkin

    John Larkin Guest


    Has anybody measured typical leakage currents for an HCT4051 analog
    mux? I'm wondering about both ESD diode leakage (ie, to rails) and
    leakage through open switches. I'm running 0 and +5V rails.

    Indications are that everybody's 0.1 uA max spec is wildly
    pessimistic, but I was wondering if anybody knows more, before I have
    to drag my butt into the lab and make actual measurements. It's a lot
    easier to sit here and type and eat bon-bons.

    We're scanning eight RTDs. A +2.5 volt reference goes through a
    precision 270 ohm resistor and gets mux'd to a selected RTD. The
    voltage drop across the RTD gets differentially mux'd, too. A 24-bit
    delta-sigma ADC digitizes the voltage drop across the 270, then the
    voltage across the RTD, and does the math. We're getting errors in the
    tens of PPM, tolerable, but we're curious where they're coming from.
    The sensitivity analysis math here is a nuisance.

  2. Jim Thompson

    Jim Thompson Guest

    The ESD diodes are probably in the <1nA range, but the switches are
    HUGE (for low on resistance), so they're likely the source of the

    ...Jim Thompson
  3. Joerg

    Joerg Guest

    Hello John,
    Actually channel-to-channel it's 0.4uA for the '51, less for the '52 and
    '53. Sez TI.

    However, the difference in RDSon from channel to channel can be up to
    10ohms or so. I have never seen that much in practice but if this
    matters can't you sink in a reference current instead of a voltage?

    And watch our for fingerprints, flux and bon-bon residue ;-)

    Regards, Joerg
  4. John Larkin

    John Larkin Guest

    Putting R(ref) and R(unknown) in series, and measuring their voltage
    drops, is a neat way to compute R(unk). The resistance range we can
    measure goes from zero to infinity, and it's purely ratiometric on a
    single super-precision resistor. Plus, we're summing the two measured
    voltages as a sanity check on the entire 4-wire loop.

    The small errors we're seeing may be due to cmos switch leakage, but
    the error TCs are looking linear enough that leakage is probably not a
    big issue... it should be sorta exponential on temperature, and we're
    not seeing that.

    Switch resistance doesn't matter here as long as it's constant for the
    duration of the two measurements. We're taking about 130 millisec for
    each measurement, 260 total. It might be that the current (about 6 mA
    when we're measuring a 100 ohm RTD) is heating the cmos switch enough
    to give it a r-versus-t curve that matters. 6 mA, 75 ohms typ, gives
    around 3 milliwatts in the switch. The HCT switch is about 75 ohms and
    increases about 0.25 ohms/K. So, what's the thermal coefficient of one
    fet in an HCT4051? 1000 k/w maybe?

    If it increases 3K as a result of the switched current, we'll have
    0.75 ohms increase, serious by our standards. But what's the thermal

  5. Guest

    The manufacturer's specified leakage current specification used to be
    set by the limitiations of their measuring gear and the time available
    to take the measurement.

    Back in 1979 I got thrown into a project to do a similar job, where the
    originator had based the design on measured leakage currents which were
    two or three orders of magnitude lower. I rejected the original design
    on the basis that the manufacturers were always at liberty to degrade
    their silicon to take advantage of the relatively sloppy leakage
    current specification, and found a nitride-insulated unprotected
    discrete MOSFET that had guaranteed leakage currents comparable with
    the measured CMOS leakage currents

    I don't know how leaky modern CMOS has become.
  6. Mark

    Mark Guest

    consider the capacitance at the input of the A/D.

    when the mux changes channels, it has to charge/discharge to the new
    value through the series resistance

    it might take a long time for the cap to reach final value accurate to
    24 bits.

    this leads to what appears to be crosstalk between the channels

    you can improve the situation by setting the mux to channel with the
    fixed ref voltage in bettween reading active channels

    it seems hard to belive a small c could do this but if you are going
    for 24 bits, it may be part of the problem

  7. john jardine

    john jardine Guest

    A few years ago did a very similar 8 way muxed RTD (4051s), for a motor
    control system. Initially ran at 8ma RTD current but on RTD selection
    'noticed' a small frequency shift on the opto isolated V to F output.
    Eventually traced to RTD heating, so dropped the constant current to 2ma.
    The spec was nowhere near to what you are resolving to so this aspect is
    probably of no consequence.
  8. Don't remeber exactly but I vaguely remember these suckers having
    different leakages (or some other characteristic) in different
    directions too? (or was it the 4066...?)
    There was some fine print in the datasheet that admitted this.
    Was quite a bad trap for my application at the time.
    They can be nasty little suckers.

    Dave :)
  9. John  Larkin

    John Larkin Guest

    I am letting things settle for about 4 milliseconds before I kick off
    the ADC, which should let RC tau's settle pretty well. Impedances are
    low here.

    Our system spec is 250 PPM, and we're getting 10's, even 1's of PPM
    for resistances near what we calibrate with, with a systematic trend
    of error versus Rx, peaking at around 100 PPM at our operating
    extremes. So we're OK, but I'd like to understand the residual errors
    and fix them. We just did a channel-channel crosstalk check, and
    changing channel N over its full resistance range affects N+1 about 1
    PPM, hard to resolve, so thermals in the cmos switch are looking

    We'll build and test a few more boards. If the errors seem systematic,
    we can always toss a little software curvature at it, and never really
    have to understand the physics.

    Y = Y + K * Y^2

    has cured more sins than the College of Cardinals.

  10. Fred Bartoli

    Fred Bartoli Guest

    I did measure an old CD4053 about two years ago (sorry did not have 74HC).
    It had +/-5V supplies and was arranged for 0V common mode at both switch
    IIRC the leakages were about 1pA at room temperature.

    One thing that surpised me was that, while static leakages were that low,
    dynamic leakages (100kHz switching) were not negligeable at all.

    Quizz: how do you pump fraction of a uA through the resistors with the
    switch wired as below?

    | | ___
    | |--|___|- GND
    ___ | o---/| 50K
    GND -|___|--|---o--__ |
    50K | o--- | ___
    | \|--|___|- GND
    '------------' 50K
  11. I think I'd investigate the possibility (probability?)
    that the current is changing during the adc measurements,
    due to the temperature coefficient of the switches.

    Perhaps modify the adc sequence to take three readings,
    V270, Vunknown, V270. See if the two V270 results are
    the same.

    If they are not, you might get away with using the
    average of the two V270 adc readings in the calcs.
  12. Jim Thompson

    Jim Thompson Guest

    On Wed, 30 Nov 2005 19:37:17 -0800, John Larkin

    Bwahahahaha! Until you get a new batch of parts.

    ...Jim Thompson
  13. Jim Thompson

    Jim Thompson Guest

    Good point, it probably IS charge injection. The measured effect of
    that WOULD vary with R value, as John seems to be seeing.

    ...Jim Thompson
  14. Fred Bartoli

    Fred Bartoli Guest

    But charge injection _alone_ can't do that. It will eventually reach
    equilibrium but it can't _alone_ have the switch 3 pins negative or positive
    all at once.

    Have a look at (or remember :) how switches are designed...
    That was surprising a first sight, but then natural, looking a bit further.

    I think John's switching frequency is way much lower, so no pb.
  15. Phil Hobbs

    Phil Hobbs Guest

    The other thing is that if any of the analogue lines goes outside the
    power supplies, all the analogue lines get connected together. Very


    Phil Hobbs
  16. "John Larkin" ...

    Have you considered the thermal gradient in the chip may cause offset
    voltages from the thermocouple like junctions (also Al-Si bonding points
    etc) in the chip? I've seen 10..100 uV offsets when a 4051 chip (turned ON)
    was next to a dissipating element. What's the equivalent offset voltage you

    Arie de Muynck
  17. John Larkin

    John Larkin Guest

    Yikes, that is a real possibility. I did note in this ng, recently,
    about thermocouple gradients in opto-ssr's!

    Assuming a couple K of self-heating in the 4051, and a few uV/K
    thermoelectric effect, we could have very roughly 10-50 (?) microvolts
    of error injected into the middle of the series resistor pair, in the
    ballpark of the error we're seeing. The error should go as i^2, which
    we can analyze to see if this is an actual candidate effect to explain
    (some of) the residual errors.

    But wait...

    r1 adc
    r2 adc

    We're doing a 4-wire voltage-drop measurement on each of the two
    resistors. So adding a potential internal to the analog switch 4051a
    in effect only changes the overall reference voltage. And the ohms
    calculation is ratiometric, so the actual voltage doesn't matter. So
    what's left is a time-domain *change* in this error component during
    the measurement process.

    This precision stuff is interesting. Very low-order effects become
    important, and they are the devil to find and quantify.

  18. Joerg

    Joerg Guest

    Hello John,
    I don't know what the leakage mechanism is, that would be Jim's domain.
    However, unless I misunderstood something then 0.4uA out of 6mA is
    already 66ppm. So a few ten ppm seems like you are getting a good deal
    from those '51 chips. If they spec them at 0.4uA max versus 0.1uA for
    the other muxes then it's unlikely you'd be getting 0.1uA from a '51.

    Maybe one way to find out is to scoot the measurement window back and
    forth a few tens of milliseconds.

    Whenever I wanted to know those kind of things from app engineers I was
    often told that such data is not available and that I should use this
    newer xyz gizmo chip. Which, of course, was an order of magnitude more

    Regards, Joerg
  19. Phil Hobbs

    Phil Hobbs Guest


    TC coefficient for silicon to any metal is about _700_uv/K_. Ugly ugly

    From your schematic, it looks as though TC offsets of sections B and C
    are not cancelled by the 4-wire ratiometric approach.


    Phil Hobbs
  20. John Larkin

    John Larkin Guest

    Ghastly. Look at the graph at the end!

    Are p-n couples used as thermal imagers?

    Yeah, but there's no current in those switches. There are three
    separate 4051's, separate packages.

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