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Ground and Ground plane on 2 layer board

Discussion in 'Electronic Design' started by Liuc, Jan 5, 2007.

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  1. Liuc

    Liuc Guest

    Hi everybody,
    I am doing a design of 2 different boards and I am struggling about the
    use (or abuse?) of the Ground Plane.
    Both the boards have a SMPS (LM2575) that generate 3.3VDC from an input
    of 12/24 V AC/DC. The CPU on the 2 boards are 8 bit microcontrollers
    (PIC18) , one running at 20 Mhz and the other at 4Mhz. No signal on
    both the boards is running faster than these frequencies.
    Both the boards have a SPI EEPROM, an RTC and a RS485 transceiver. The
    20Mhz board has 4 relay outputs and 4 optoisolated inputs, whilst the 4
    Mhz board has only 1 relay output.
    The boards are both routed 95% on the top layer, I use the bottom only
    for VCC and GND and for few lines that I wasn't able tofit on the top

    My question is: how to use the ground plane? I've read plenty of
    threads about it, but I didn't fully understand which is the best way
    to do. My doubts are mainly about:

    1) GND of the SMPS: the SMPS is located in a definite area of the PCB,
    so I made a GND plane "all for it", and connected to the rest of GND
    plane in a single point witha thick trace. Is it correct or is it
    better to make a big plane for all the pcb?
    2) GND of the relays: I made a GND line only for relays , and connected
    it with the GND plane only in one point. Correct or not? (in the relay
    area there is no GND plane at all, top and bottom layers)
    3) grounding of the RTC (DS1302): should I take particular precautions
    about the GND plane surrounding the RTC and its crystal? (also about
    the 20Mhz crystal)
    4) FUll or grid gnd plane? For my pcb manifacturer it's the same, so I
    have to choose...

    more generally speaking, not having RF stages on my boards, once
    finished the routing I filled in almost all the unused PCB area with a
    GND plane, both top and bottom layer. Of course I was checking that I
    had as few interruptions as possible, specially on the bottom layer,
    even if I need to have some (for Vcc and for the 5% of routing descrbed
    But is this a correct approach or I am making everything wrong? Should
    I use only the bottom layer for the GND plane? or is ok to fill
    everything fillable? :)

    I know that using a 4 layer board would make everything easier, but I
    have to keep my design in a 2 layer... no way to change this!

    I think that's all, sorry for the lenght of this thread but I wanted to
    put out all my doubts, so that maybe it can be useful also for other

    Thanks since now to everybody who can help, all the best,

  2. Mr. Wizard

    Mr. Wizard Guest

    Using a single point ground that you are using should be fine. Make
    sure that you try and locate this star ground as close to the exit
    point on the PCB. If you check out National's website for app notes
  3. Noway2

    Noway2 Guest

    Speaking generally and not getting into the specifics of your design:

    The purpose of the power (ground) system is to provide a constant
    voltage supply to your logic circuit. This supply must present the
    constant voltage in the presence of varying and surging currents caused
    by the electronic switching. In order to maintain this regulation, the
    power (ground) system must have a very low impedance across a fairly
    significant bandwidth. The exact bandwidth that you need to be
    concerned about depends not so much on the clock rate of your circuit
    (the 20Mhz and 4MHz that you mention) but the rise and fall times of
    the digital signals. Providing the constant voltage, low impedance
    supply is often accomplished through proper use of decoupling
    capacitors. You didn't mention them in your design, but if this
    concept is new to you then you should investigate it.

    Many, especially novice, designers also forget about the return
    currents. When they look at a circuit schematic they see a driver
    connecting to a receiver and the current path between them is obvious.
    What is not as obvious is that there is also a return current, through
    the 'ground' path between the devices. The ground path needs to be as
    low of an impedance as the power path. The only structure that will
    provide a sufficiently low impedance for the ground is a wide flat
    structure, or a plane. The reason being that at the frequencies of
    interest, which as I pointed our earlier are far greater than your
    clock rate, the impedance of the ground becomes dominated by the
    inductance and to get a low inductance (impedance) you need a wide flat
    structure. A ground plane that is full of holes is still infinately
    better than a serpentine trace.

    A copper pour will work for a ground plane. On your board which is two
    layer, it probably matters little wether the plane is on the top or
    bottom side of the board. If you are planning on wave soldering the
    board, you may want to consider putting the ground plane on the 'top'
    as it is possible for the board to warp when it is exposed to the wave
    solder, though this is a more minor consideration.

    Regarding the point about a single ground connectiont that was
    mentioned, you want to keep in mind how current will flow. The idea is
    to avoid multiple ground paths into or out of a circuit or region of
    the board as these cause ground loops which can cause ground voltage
    differences in the board and open the window for EMI.
  4. Liuc

    Liuc Guest

    Hi Noway2,
    first of all thaks to you and to Mr. Wizard for your answers.
    About what you wrote, you are right: I forgot to write about dec
    capacitors. I am using a 100nF capacitor (ceramic multilayer) on each
    Vcc pin of the ICs used in the 2 boards.

    I still have a question: how can I estimate correctly the bandwith "to
    be concerned about" about my digital signals? I mean, the digital
    signals involved in my boards are:

    lines for relay switching -> very slow switching
    line for inputs -> also there I think the signal is enough slow

    serial communications:

    rs485, working at 9600bps
    I2C and 1Wire bus, same speed

    so which is the correcnt approach to estimate bandwith for the
    impedance of the ground (power) system?

    thanks again


    Noway2 ha scritto:
  5. Paul Mathews

    Paul Mathews Guest

    The most useful concept to understand is 'loop area', part of which is
    the idea of 'return currents', as discussed in another msg this thread.
    By minimizing loop area, you will be minimizing inductances. Large
    copper pours, including ground planes, provide one way of minimizing
    loop areas. However, on a 2-layer board, it can be difficult to avoid
    cutting up the ground pour, so that there are numerous 'moats' and
    'slots'. Study this subject until you understand why such features
    should be avoided where possible and how you can route traces on the
    other layer so that return currents are not forced to go around the
    moats and slots. Keywords for your search are: circuit board, layout,
    inductance, loop area, moat, slot. There are also many excellent
    articles and books by authors including: Mark Montrose, Howard Johnson,
    Sanjaya Maniktala.
    Paul Mathews
  6. John  Larkin

    John Larkin Guest

    Since your board doesn't have any low-level analog stuff, you may as
    well just pour solid copper on the bottom side. You'll certainly also
    need some signals on the bottom, so arrange for them to be generally
    short so the ground plane isn't terribly chopped up by their
    clearances, which it sounds like you've done. There's no advantage to
    deliberately sectioning the ground plane into regions for different
    functions and it can cause problems. The whole "star grounding" thing
    is mostly popular superstition.

    Pouring topside ground usually doesn't help, as all you wind up with
    is a lot of slivers of copper not doing much except making
    solder-bridge shorts and being confusing in general.

    I could post a couple of pics to a.b.s.e.

  7. Noway2

    Noway2 Guest

    To estimate the bandwidth of a digital signal, you can use a concept
    called the knee frequency. Roughly speaking, the knee frequency is the
    point (frequency) at which the energy content of the signal starts to
    drop off significantly. When you use the knee frequency concept, you
    can't treat it as a hard and fast rule, but it can tell you if you are
    in the clear, have something to consider, or have an outright problem.

    If I remember correctly, the formula for the knee frequency that I use
    is 0.5 / Trise (in ps), which is the formula I picked up from Dr.
    Howard Johnson's book. There are probably other definitions. So if
    your logic signal transisitions in 2ns (2000 ps) the Fknee is .5 / 2000
    x10-12 or 250Mhz. This means that in order to avoid distorting the
    signal edges, which can be critical in digital systems, you need to
    make sure that your board is capable of handling an effective bandwidth
    of 250Mhz as there will be significant engery content below this point.

    To understand why there is energy content up to this point, think of a
    Fourier representation of a digital pulse, which consists of a sum of
    odd harmonics. The higher order harmonics are what gives the pulse its
    sharp edges and hence the sharper the edges, the greater the
    significance of the higher order harmonics.

    These concepts also get into why when you probe a circuit that you
    alter its behavior and why your o-scope isn't necessarilly giving you
    an accurate picture. If you have a scope with a 100Mhz bandwidth you
    will be missing the higher frequency effects.
  8. Joel Kolstad

    Joel Kolstad Guest

    I believe Howard uses 0.35/Tr with the stated assumption of a Gaussian
    frequency response in the measurement system. With contemporary instruments,
    this is sometimes a little overly pessimistic... see, e.g.,
  9. Rich Grise

    Rich Grise Guest

    There aren't really any hard and fast rules - one thing to keep in mind is
    current paths. Current always flows from the power supply through the load
    (your circuit) and back. When you're laying out your power supplies and
    parts, visualize which copper will have the current flowing from and to
    the supply, and try to minimize the interaction between those current
    flows for different supplies. I think this is the idea behind the "single
    point" or "star" ground. If you watch your layout, that shouldn't be
    necessary. Where is the current flowing is what you need to watch.

    Also, I've always said you can't overcapacitate. 10uF or more at the power
    entry point and a .1 ceramic (or more, depending on power/ground pins) at
    each chip has always worked for me. :)

    Good Luck!
  10. Mr. Wizard

    Mr. Wizard Guest

  11. Rich Grise

    Rich Grise Guest

  12. Liuc

    Liuc Guest

    Hi again,
    and thanks to eveybody who answered me: particulary to the posts about
    signal bandwidth.
    Now I don't have cleared all my doubts but I have things more clear.

    thanks again,


    Noway2 ha scritto:
  13. John Perry

    John Perry Guest

    I recall having seen this relation in Tektronix application notes
    relating the bandwidth of a scope to the minimum distinguishable rise
    time of that scope in the early 70's. The caveat about Gaussian
    frequency response sounds familiar, too.

    John Perry
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