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GDDR5 addressing

Discussion in 'Datasheets, Manuals and Component Identification' started by r4space, Jun 24, 2014.

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  1. r4space

    r4space

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    Jun 24, 2014
    Hi,

    I'm trying to develop a GDDR5 controller and am slightly confused regarding the JDEC spec document - the different memory configuration possibilities all seem to be short three address bits to attain the capacity specified...?

    For example 512M memory, 32x mode, with 16 banks:
    Row address bits are A0-A11 (12)
    Column address bits are A0-A5 (6)
    Bank address bits are: BA0-BA2 (3)
    (See JDEC spec document JSED212B.01 pg 12 Table 7 and Table8)

    But that only addresses 2^12*2^6*2^3=2Mi addressed locations each of x32bits = 64Mbs....

    You can do the same with any other configuration listed and still not get the capacity specified. This isn't related to bank groups or the fact that GDDR5 multiplexes it's address lines but clearly there's something else non-standard (different to DDR3) that I'm missing?

    Anyone with insights please advise?
     
  2. Harald Kapp

    Harald Kapp Moderator Moderator

    10,554
    2,353
    Nov 17, 2011
    You've cross posted the identical question on 2 other forums. That's bad netiquette.

    You should at least link to the JEDEC document, don't expect this to sit around on everybody's boookshelf.

    You contradict yourself in the question. First you write ...16 banks, then you gon on with bank address bits BA0...BA2 (3) which gives you 8 banks only.
     
  3. r4space

    r4space

    3
    0
    Jun 24, 2014
    Sorry about the typo (bad example): There are 16 banks in all configurations larger than 512, 8 in the 512.

    Re-posting because there's no obvious forum in which to ask this and I'm not expecting the same selection of people to follow all 3 forums.

    JEDEC standard is behind a registration login but is free here:
    http://www.jedec.org/standards-documents/results/GDDR5
     
  4. r4space

    r4space

    3
    0
    Jun 24, 2014
    I couldn't find this information anywhere so in case someone else needs it linking to where is was answered very nicely! If that's in appropriate maybe the moderators can delete this whole thread.

    http://www.tomshardware.com/answers/id-2194505/gddr5-memory-addressing.html

    In brief GDDR5 burst access is limited to a single column address making an address location equivalent to x32*8 burst length bits in size.
     
  5. Harald Kapp

    Harald Kapp Moderator Moderator

    10,554
    2,353
    Nov 17, 2011
    Thanks for the link, obviously no one here had the ressources to answer the question, sorry.
     
  6. davenn

    davenn Moderator

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    1,891
    Sep 5, 2009
    sorry as well ... tis outside my field of expertise


    Dave
     
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