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gated pulse stream problem

S

Slim Gaillard

Jan 1, 1970
0
I have a continuous stream of 10us square pulses with a period of
50us coming from a signal generator. I'd like to select bursts of
N of these pulses to send on to another instrument by combination
of the pulse stream with a gate signal in an AND gate. The pulse
stream and the gate come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes
N+1 pulses (a runt at the beginning and the end of the gate, and
a full pulse in the middle). If I make the gate N*50-10us wide, I
get sometimes N, sometimes N-1 pulses. Is there some way to do
this so that I always get N pulses?

thanks! slim
 
J

Jamie

Jan 1, 1970
0
Slim said:
I have a continuous stream of 10us square pulses with a period of 50us
coming from a signal generator. I'd like to select bursts of N of these
pulses to send on to another instrument by combination of the pulse
stream with a gate signal in an AND gate. The pulse stream and the gate
come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes N+1
pulses (a runt at the beginning and the end of the gate, and a full
pulse in the middle). If I make the gate N*50-10us wide, I get sometimes
N, sometimes N-1 pulses. Is there some way to do this so that I always
get N pulses?

thanks! slim
Pass the sum to a flip flip?
this obvious will scale the output by half.
also, an Xor gate seems to come to mind on this for
some reason.


http://webpages.charter.net/jamie_5"
 
I have a continuous stream of 10us square pulses with a period of
50us coming from a signal generator. I'd like to select bursts of
N of these pulses to send on to another instrument by combination
of the pulse stream with a gate signal in an AND gate. The pulse
stream and the gate come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes
N+1 pulses (a runt at the beginning and the end of the gate, and
a full pulse in the middle). If I make the gate N*50-10us wide, I
get sometimes N, sometimes N-1 pulses. Is there some way to do
this so that I always get N pulses?

Use a - say - 15usec monstable triggered on the leading edge of your
10usec pulse to block the gate signal, and a second - say - 45usec
monstable triggered at the same point to create a 30usec wide window
where you can turn on your gating signal in the certain knowledge that
it isn't going to chop any of your 10usec pulses in half.

You will need to work out worst case tolerances on your monostable
output transitions vis-a-vis your 10usec pulse edges, and if the clock
controlling your 10usec pulse width and your 50usec pulse period isn't
the same clock that controls with width of your gating signal you will
have to work out how large you can let N be before the position of the
trailing edge of the gating signal becomes uncertain enough to risk
getting into one of the 10usec pulses.

If the clock available in the system that generates your gating signal
is fast enough, you can use triggered counters to replace the two
monostables.
 
J

Jasen Betts

Jan 1, 1970
0
I have a continuous stream of 10us square pulses with a period of
50us coming from a signal generator. I'd like to select bursts of
N of these pulses to send on to another instrument by combination
of the pulse stream with a gate signal in an AND gate. The pulse
stream and the gate come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes
N+1 pulses (a runt at the beginning and the end of the gate, and
a full pulse in the middle). If I make the gate N*50-10us wide, I
get sometimes N, sometimes N-1 pulses. Is there some way to do
this so that I always get N pulses?

thanks! slim


use a D-type falling-edge-triggered flip-flop to synchronise
your gate signal __
.----------------------------| \
| _____ | & |---- out
Pulse source -------------+----|clk | .-|__/
| | |
gate source -(60us one-shot)----|D Q|---(one shot)--'
`-----' adjust for N pulses
 
B

Ben Jackson

Jan 1, 1970
0
use a D-type falling-edge-triggered flip-flop to synchronise
your gate signal __
.----------------------------| \
| _____ | & |---- out
Pulse source -------------+----|clk | .-|__/
| | |
gate source -(60us one-shot)----|D Q|---(one shot)--'
`-----' adjust for N pulses
That will produce a trailing glitch when the turn-off pulse arrives.
It will sneak out the AND gate until the propagation delay of the FF+AND
turn it off. Someone else suggested the same arrangement but with the
clk input inverted, which makes more sense.
 
R

Rich Grise

Jan 1, 1970
0
On Mon, 15 Dec 2008 20:17:09 -0500, Slim Gaillard


If the gate must be used to count the pulses, probably not. The gate
rising edge cound be used to start a hunk of synchronous logic that counts
out exactly 50 clean pulses.
A resynchronizer? Don Lancaster had one of these in the TTL cookbook.

Cheers!
Rich
 
J

Jasen Betts

Jan 1, 1970
0
That will produce a trailing glitch when the turn-off pulse arrives.
It will sneak out the AND gate until the propagation delay of the FF+AND
turn it off. Someone else suggested the same arrangement but with the
clk input inverted, which makes more sense.

the second one-shot monostable should not turn off until after the final pulse.
(but before the next pulse)
 
J

Jasen Betts

Jan 1, 1970
0
That will produce a trailing glitch when the turn-off pulse arrives.
It will sneak out the AND gate until the propagation delay of the FF+AND
turn it off. Someone else suggested the same arrangement but with the
clk input inverted, which makes more sense.

the second one-shot monostable should not turn off until after the final pulse.
(but before the next pulse)


the first one-shot is optional as long as the gate signal is goes high
(and low) for long enough for the flip-flop to switch.

here's a demo (I built the one-shot from real parts)

there's a bunch of labeled nodes with shifted and scaled voltages that
make a pretty timing diagram in the scope window.

Version 4
SHEET 1 2020 724
WIRE -336 -160 -400 -160
WIRE 1696 -160 1632 -160
WIRE -400 -112 -400 -160
WIRE -336 -112 -336 -160
WIRE 1632 -112 1632 -160
WIRE 1696 -112 1696 -160
WIRE -288 -32 -336 -32
WIRE 1744 -32 1696 -32
WIRE -544 -16 -608 -16
WIRE -608 32 -608 -16
WIRE -544 32 -544 -16
WIRE -160 48 -336 48
WIRE 1696 48 -160 48
WIRE 1776 48 1696 48
WIRE 1952 48 1840 48
WIRE 2016 48 1952 48
WIRE 1952 64 1952 48
WIRE -336 80 -336 48
WIRE 1184 80 880 80
WIRE 1712 80 1184 80
WIRE 1776 80 1712 80
WIRE 816 96 464 96
WIRE 1184 96 1184 80
WIRE -496 112 -544 112
WIRE 1952 128 1936 128
WIRE 32 144 -256 144
WIRE 224 144 192 144
WIRE 240 144 224 144
WIRE 336 144 304 144
WIRE 1712 144 1712 80
WIRE 544 160 512 160
WIRE 864 160 768 160
WIRE 912 160 864 160
WIRE 960 160 912 160
WIRE 1184 160 1168 160
WIRE 512 176 512 160
WIRE 960 176 960 160
WIRE -160 192 -160 48
WIRE -80 192 -160 192
WIRE 32 192 -16 192
WIRE -544 208 -544 192
WIRE -384 208 -544 208
WIRE -256 208 -256 144
WIRE -256 208 -384 208
WIRE -384 224 -384 208
WIRE 544 224 432 224
WIRE 832 224 768 224
WIRE 1952 224 1952 208
WIRE 1184 256 1184 240
WIRE 464 288 464 96
WIRE 544 288 464 288
WIRE 832 288 832 224
WIRE 832 288 768 288
WIRE 224 320 224 144
WIRE 832 320 832 288
WIRE 864 320 864 240
WIRE 864 320 832 320
WIRE 1952 320 1952 304
WIRE 224 336 224 320
WIRE 432 352 432 224
WIRE 544 352 512 352
WIRE 1184 352 1184 336
WIRE 224 400 208 400
WIRE 336 400 336 144
WIRE 368 400 336 400
WIRE 512 400 512 352
WIRE 912 400 912 160
WIRE 912 400 512 400
WIRE 832 416 832 320
WIRE 608 448 432 448
WIRE 624 448 608 448
WIRE 224 496 224 480
WIRE 336 496 336 480
WIRE 416 496 336 496
WIRE 608 496 608 448
WIRE 608 496 496 496
WIRE 832 496 832 480
WIRE 832 496 608 496
WIRE 832 512 832 496
WIRE 224 592 224 576
FLAG -336 160 0
FLAG -384 304 0
FLAG -400 -32 0
FLAG -288 -32 pulse_clock
FLAG -608 112 0
FLAG -496 112 trigger_clock
FLAG 224 592 0
FLAG 208 400 flop_out
FLAG 512 176 0
FLAG 960 256 0
FLAG 832 512 0
FLAG 1184 352 0
FLAG 1168 160 mono_out
FLAG 1952 320 0
FLAG 1936 128 output
FLAG 1632 -32 0
FLAG 1744 -32 pulse_clock2
FLAG 352 -192 pulse_clock
FLAG 352 -160 pulse_clock2
FLAG 352 -128 trigger_clock
FLAG 352 -96 flop_out
FLAG 352 -64 mono_out
FLAG 352 -32 output
SYMBOL voltage -336 64 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 .00001 .00006)
SYMBOL Digital\\and 1808 0 R0
SYMATTR InstName A1
SYMBOL Digital\\dflop 112 96 R0
SYMATTR InstName A2
SYMBOL voltage -384 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 0 0 .000084 .0006141)
SYMBOL res -352 -48 R0
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL res -352 -128 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage -400 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL res -560 96 R0
SYMATTR InstName R3
SYMATTR Value 12K
SYMBOL res -560 16 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage -608 16 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value .9v
SYMBOL res 240 416 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R5
SYMATTR Value 12K
SYMBOL res 240 496 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage 224 480 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value .8v
SYMBOL Digital\\inv -80 128 R0
SYMATTR InstName A3
SYMBOL cap 304 128 R90
WINDOW 0 0 32 VBottom 0
WINDOW 3 32 32 VTop 0
SYMATTR InstName C1
SYMATTR Value 10n
SYMBOL Misc\\NE555 656 256 R0
SYMATTR InstName U1
SYMBOL voltage 960 160 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value 5v
SYMBOL cap 816 416 R0
SYMATTR InstName C2
SYMATTR Value 40n
SYMBOL res 848 144 R0
SYMATTR InstName R7
SYMATTR Value 7.3K
SYMBOL npn 368 352 R0
SYMATTR InstName Q1
SYMBOL res 528 336 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 1k
SYMBOL res 320 384 R0
SYMATTR InstName R10
SYMATTR Value 4K
SYMBOL voltage 400 496 R270
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V7
SYMATTR Value .4v
SYMBOL Digital\\buf 816 32 R0
SYMATTR InstName A4
SYMBOL res 1200 176 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R9
SYMATTR Value 12K
SYMBOL res 1200 256 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R11
SYMATTR Value 1k
SYMBOL voltage 1184 240 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value .7v
SYMBOL res 1968 144 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R12
SYMATTR Value 12K
SYMBOL res 1968 224 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R13
SYMATTR Value 1k
SYMBOL voltage 1952 208 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value .6v
SYMBOL res 1680 -48 R0
SYMATTR InstName R14
SYMATTR Value 12K
SYMBOL res 1680 -128 R0
SYMATTR InstName R15
SYMATTR Value 1k
SYMBOL voltage 1632 -128 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V10
SYMATTR Value .5
TEXT -418 332 Left 0 !.tran .01
TEXT 280 -232 Left 0 ;probe thses nodes to get a timing diagram in the scope
 
S

spamme9

Jan 1, 1970
0
Slim said:
I have a continuous stream of 10us square pulses with a period of 50us
coming from a signal generator. I'd like to select bursts of N of these
pulses to send on to another instrument by combination of the pulse
stream with a gate signal in an AND gate. The pulse stream and the gate
come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes N+1
pulses (a runt at the beginning and the end of the gate, and a full
pulse in the middle). If I make the gate N*50-10us wide, I get sometimes
N, sometimes N-1 pulses. Is there some way to do this so that I always
get N pulses?

thanks! slim

What are you trying to accomplish?

In the general case, it can't be done.

There are many ways to synthesize a gate that lets exactly 50
pulses through, but then it's not the gate you started with.
Might as well just use a trigger to generate 50 pulses.
And if you're gonna do that, might as well just
skip the hardware and assume you
got 50 pulses and be done with it...inputcounter = inputcounter + 50

If there's some timing relationship between the two sources
that you're trying to preserve, you need to specify what you want.

And we haven't even started thinking about what to do with the
race condition when the two edges are coincident...give or take a little.

So, what are you trying to accomplish? 90% of the solution is deciding
what the problem is...
 
P

petrus bitbyter

Jan 1, 1970
0
Slim Gaillard said:
I have a continuous stream of 10us square pulses with a period of 50us
coming from a signal generator. I'd like to select bursts of N of these
pulses to send on to another instrument by combination of the pulse stream
with a gate signal in an AND gate. The pulse stream and the gate come from
2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get sometimes
N pulses at the output of the AND gate, and sometimes N+1 pulses (a runt
at the beginning and the end of the gate, and a full pulse in the middle).
If I make the gate N*50-10us wide, I get sometimes N, sometimes N-1
pulses. Is there some way to do this so that I always get N pulses?

thanks! slim

In the first place you'd better take a gate timing of N*50+5 or N*50-45.
This way, only one of the gate timing edges can interfere with the a clock
edge.

From the top of my had, I remember I solved a similar problem with the
circuit below.

clock--+--------------------------------------+
| |
gate---)-------------+ |
| __ | .---. .---. | __ __
+--+--| | +-|D |------|D |----+ +--| | +-| |
| |& |o-+---|> | +-|> | | |& |o-+ |& |o--burst
+--|__| | | |o- | | |o- +-----|__| +-|__|
| '---' | '---'
+------------+
created by Andy´s ASCII-Circuit v1.24.140803 Beta www.tech-chat.de

Speaking old TTL circuits, a 7400 and a 7474 will do the trick. There is a
delay as two flipflops are used. This is done to prevent glitches when the
gate timing signal changes during the setup time of the first flipflop.

petrus bitbyter
 
S

Slim Gaillard

Jan 1, 1970
0
Slim said:
I have a continuous stream of 10us square pulses with a period of 50us
coming from a signal generator. I'd like to select bursts of N of these
pulses to send on to another instrument by combination of the pulse
stream with a gate signal in an AND gate. The pulse stream and the gate
come from 2 different non-synchronized systems.

The trouble is this: if I make the gate signal N*50us wide I get
sometimes N pulses at the output of the AND gate, and sometimes N+1
pulses (a runt at the beginning and the end of the gate, and a full
pulse in the middle). If I make the gate N*50-10us wide, I get sometimes
N, sometimes N-1 pulses. Is there some way to do this so that I always
get N pulses?

thanks! slim

To clarify a bit: the system generating the pulse stream (system
A) runs at its own, stable, frequency. System B generates a gate
which is asynchronous to system A to say: "give me the next N
pulses from system A." The only way I have of specifying the
number of pulses N is through the width of the gate.

A lot of you suggested using a synchroniser based on a flip-flop
and a AND gate. This would seem to work just fine, all I have to
do is generate a gate that is N*period wide (N=2 here):

_____|¨|_____|¨|_____|¨|_____|¨|_____|¨|_____|¨| pulses
¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_|¨¨¨¨¨|_| pulses' A
__________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|_____________________ gate
_____________|¨¨¨¨¨¨¨¨¨¨¨¨¨¨¨|__________________ sync'd gate B
_______________|¨¨¨¨¨|_|¨¨¨¨¨|__________________ A & B

I'm using a falling edge triggered D flip-flop to do the
synchronising, and inverting the pulses going into it.

This gives me 2 rising or 2 falling edges in the output to
trigger on, which is OK. But what happens, as some have
suggested, when the rising edge of the gate happens to coincide
with a falling pulse' edge (and its falling edge therefore
coincides with another)? It looks like, no matter what i do in
this case, I'm back to the problem of having one more, or one
less, trigger edge in the output than I want. Or can the addition
of delays, as others have suggested, get around this problem somehow?




_______________|¨|_____|¨|
 
S

Slim Gaillard

Jan 1, 1970
0
John said:
---
I've posted a simple four chip solution for you on
alt.binaries.schematics.electronic which I'm pretty sure will work.

Do you need a circuit description?
JF

What is the general idea behind it (my experience with logic
circuits is nil+epsilon, so I can't read a schematic like yours
in detail)? It looks like you're using a counter (pre-programmed
with N, I suppose?) Does that mean you agree that the problem is
insoluble using only the width of the gate to determine the
number of pulses in a burst?
 
S

Slim Gaillard

Jan 1, 1970
0
Jim said:
I think my posted schematic will always give you N pulses. It may
just take as much as a CLK period to start the first output pulse.

...Jim Thompson

You fall in the "it's possible" camp, then. But you use a shift
register instead of a flip-flop? It looks like the gate AND will
be turned on one clock pulse after the select signal goes high,
but then turn off again after 7 pulses, no matter if the select
signal stays high or not (as soon as the input signal is shifted
down to QH)?
 
S

Slim Gaillard

Jan 1, 1970
0
Jim said:
How many pulses do you wish per burst? Did you look at what I posted?

...Jim Thompson

Yes, thank you for the schematic. I need 1 to maybe 1024 pulses
per burst, selectable through adjustment of the width of the gate.
 
S

Slim Gaillard

Jan 1, 1970
0
Jim said:
So you want pulses as long as your "command" is high, just not
truncate on either end?

Is that correct?

My original reading was that you wanted to specify a constant "N"??

You can simply add SR stages to lengthen "N" for my original post.

You can do this with a counter (flip-flops), but cautiously, to avoid
glitches/slivers.

...Jim Thompson

Right, I want to control the number of pulses per burst by
changing the width of the gate pulse. I see on the Wikipedia
entry for flip-flops that using two of them minimizes the
probability of the problems encountered when the gate signal
happens to come at the same time as a clock signal
(glitches/slivers?). I guess this iw what Jason Betts was
suggesting, and I will probably try this initially. The shift
register trick is a good one for small bursts. thanks, slim
 
S

spamme9

Jan 1, 1970
0
Slim said:
Yes, thank you for the schematic. I need 1 to maybe 1024 pulses per
burst, selectable through adjustment of the width of the gate.

You keep adding requirements without stating what you're trying to
accomplish
or the constraints/precision/accuracy of the timing relationships
between your clock, gate and whatever other unstated stuff is going
on in the system.

It is quite usual for a designer to become fixated on solving some
sub-problem when taking a step back would yield a much simpler overall
solution.

If you're set on using the gate thingie, you can delay the gate by
the time between gate start and the first pulse to be gated.
You accumulate delay time at the beginning and add it back on the end.
You can do this analogly with a capacitor or digitally with a
counter and a faster clock. Depending on the constraints you have
or place on your signals, you may not need many bits of counter.

Also depends on whether you have control over how the gate is generated.
Can it be ANY width? Or does it have discrete steps that can be relied
on when deriving the delayed-gate?

Sometimes, it's easier to bite the bullet and make a state
machine out of a GAL20V8.
A 20v8 makes a dandy oscillator, counter and control logic.
Clock frequency accuracy is not important, cause you're only
interested in equal times in and out.
I like 20V8's/22V10's 'cause they can be programmed with free tools
and no experience...and they come in packages that don't
require a microscope to see. And I have a lifetime supply of them.
There are surely "better" devices available if you have the
tools to use them.

Single chip processor is another option. Once you decide
to add one, many other system options become possible.
Doesn't take very many "cheap" discrete parts to increase
system cost well beyond the cost of a processor.

Much depends on what you're trying to accomplish, how
many you're going to build and your preference toward
spending more time or more money on development.
 
J

Jasen Betts

Jan 1, 1970
0
I see on the Wikipedia
entry for flip-flops that using two of them minimizes the
probability of the problems encountered when the gate signal
happens to come at the same time as a clock signal
(glitches/slivers?).
I guess this iw what Jason Betts was
suggesting, and I will probably try this initially. The shift
register trick is a good one for small bursts. thanks, slim

that's part of what I was saying... my other circut was another
fixed-length one

Right, I want to control the number of pulses per burst by
changing the width of the gate pulse.

I was thinking you might be wanting that!

To do that you need a scale to measure the length of the gate pulse
against, a scale that is finer than the pulses you are trying to gate.
, one way to do this ould be to use a clock that runs faster
than the pulse signal and an up-down counter.

I used a clock that's exactly three times the speed of your pulse clock
and phase locked. - easiest way to get that is to generate both from
the same source, anyway here's the ltspice schematic.

I only count the early part of the gate pulse (the part that arrives
before the first clock pulse is emitted) and then I tack that much
extra time onto the end of the trigger pulse.

It's quite possible that this can be done with fewer parts, I stopped
when it was working in simulation and reasonably tidy looking


Version 4
SHEET 1 2120 1220
WIRE 1344 48 -336 48
WIRE 1456 48 1408 48
WIRE 1952 48 1456 48
WIRE -336 64 -336 48
WIRE 1296 80 848 80
WIRE 1344 80 1296 80
WIRE -336 160 -336 144
WIRE -256 208 -368 208
WIRE 1456 208 1456 48
WIRE 1520 208 1456 208
WIRE -368 224 -368 208
WIRE -256 224 -256 208
WIRE 416 224 -256 224
WIRE 608 224 480 224
WIRE 688 224 672 224
WIRE -64 240 -208 240
WIRE 608 256 544 256
WIRE 1520 256 1456 256
WIRE 1664 256 1632 256
WIRE -208 288 -208 240
WIRE -192 288 -208 288
WIRE -368 304 -384 304
WIRE -256 320 -256 224
WIRE -192 320 -256 320
WIRE -112 320 -128 320
WIRE -64 320 -64 240
WIRE 544 320 544 256
WIRE 544 320 -64 320
WIRE 656 320 544 320
WIRE 688 368 688 224
WIRE 1456 368 1456 256
WIRE 1456 368 688 368
WIRE 1664 400 1664 256
WIRE 1664 400 -64 400
WIRE -256 448 -256 320
WIRE 16 448 -256 448
WIRE 96 448 80 448
WIRE 96 464 96 448
WIRE 1824 464 880 464
WIRE -64 480 -64 400
WIRE 16 480 -64 480
WIRE 192 480 160 480
WIRE 416 480 352 480
WIRE 640 480 576 480
WIRE 848 480 848 80
WIRE 848 480 640 480
WIRE 1616 496 1552 496
WIRE -112 528 -112 320
WIRE 16 528 -112 528
WIRE 96 528 80 528
WIRE 192 528 176 528
WIRE 416 528 400 528
WIRE 656 528 656 320
WIRE 656 528 592 528
WIRE 1424 544 1424 528
WIRE 1552 544 1552 496
WIRE 1616 544 1616 496
WIRE 16 560 -16 560
WIRE -16 592 -16 560
WIRE 608 592 -16 592
WIRE -304 608 -480 608
WIRE 176 608 176 528
WIRE 176 608 -240 608
WIRE 640 624 640 480
WIRE 640 624 -16 624
WIRE 1424 624 1408 624
WIRE 1664 624 1616 624
WIRE -480 640 -480 608
WIRE -384 640 -432 640
WIRE -304 640 -320 640
WIRE -384 672 -416 672
WIRE -16 672 -16 624
WIRE 16 672 -16 672
WIRE 80 688 80 672
WIRE 96 688 80 688
WIRE -64 704 -64 480
WIRE 16 704 -64 704
WIRE 192 704 160 704
WIRE 416 704 352 704
WIRE 608 704 608 592
WIRE 608 704 576 704
WIRE -416 720 -416 672
WIRE -64 720 -64 704
WIRE -64 720 -416 720
WIRE 1616 720 1616 704
WIRE -112 752 -112 528
WIRE 16 752 -112 752
WIRE 96 752 80 752
WIRE 176 752 176 608
WIRE 192 752 176 752
WIRE 400 752 400 528
WIRE 416 752 400 752
WIRE 1424 752 1424 704
WIRE 1488 752 1488 704
WIRE 1488 752 1424 752
WIRE -432 768 -432 640
WIRE -112 768 -112 752
WIRE -112 768 -432 768
WIRE 992 768 928 768
WIRE 1280 768 1264 768
WIRE 1408 768 1280 768
WIRE 16 784 -16 784
WIRE 928 816 928 768
WIRE 992 816 992 768
WIRE 1408 816 1408 768
WIRE 1408 816 1392 816
WIRE -16 832 -16 784
WIRE 640 832 -16 832
WIRE 1536 832 1520 832
WIRE 1280 848 1280 768
WIRE 1280 848 1264 848
WIRE 1696 848 1696 832
WIRE 1696 848 1680 848
WIRE 608 864 608 704
WIRE 608 864 -16 864
WIRE 1040 896 992 896
WIRE 1408 912 1408 896
WIRE 1536 928 1536 912
WIRE -16 944 -16 864
WIRE 16 944 -16 944
WIRE 192 944 80 944
WIRE 208 944 192 944
WIRE 416 944 352 944
WIRE 432 944 416 944
WIRE 640 944 640 832
WIRE 640 944 576 944
WIRE 1280 944 1280 848
WIRE 1280 944 1264 944
WIRE -64 976 -64 720
WIRE 16 976 -64 976
WIRE 176 992 176 752
WIRE 192 992 176 992
WIRE 400 992 400 752
WIRE 416 992 400 992
WIRE 1280 992 1280 944
WIRE 1408 1008 1408 992
WIRE 1696 1008 1696 992
WIRE 1536 1024 1536 1008
WIRE 880 1056 880 464
WIRE 1184 1056 880 1056
WIRE 1824 1056 1824 464
WIRE 1824 1056 1184 1056
WIRE 176 1088 176 992
WIRE 256 1088 176 1088
WIRE 400 1088 400 992
WIRE 400 1088 320 1088
FLAG -336 160 0
FLAG -384 304 0
FLAG 928 896 0
FLAG 1040 896 pulse_clock
FLAG 1552 624 0
FLAG 1664 624 trigger_clock
FLAG 1696 1008 0
FLAG 1680 848 sync_out
FLAG 1536 1024 0
FLAG 1520 832 output
FLAG 1488 624 0
FLAG 1408 624 pulse_clock2
FLAG 352 -192 pulse_clock
FLAG 352 -160 pulse_clock2
FLAG 352 -128 trigger_clock
FLAG 352 -96 ctr_state
FLAG 352 -64 sync_out
FLAG 352 -32 output
FLAG -480 720 0
FLAG 1408 1008 0
FLAG 1392 816 ctr_state
FLAG 1536 752 out
FLAG 1952 48 out
FLAG 1296 80 sync
FLAG 1696 752 sync
FLAG 640 480 ctr1
FLAG 1184 768 ctr1
FLAG 1184 848 ctr2
FLAG 608 704 ctr2
FLAG 640 944 ctr3
FLAG 1184 944 ctr3
FLAG -336 48 Pulses
FLAG 992 976 Pulses
FLAG -256 208 trigger
FLAG 1616 720 trigger
FLAG -480 608 timer
FLAG 1424 528 timer
FLAG 1184 1056 0
SYMBOL voltage -336 48 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 .00001 .00006)
SYMBOL Digital\\and 1376 0 R0
SYMATTR InstName A1
SYMBOL voltage -368 208 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 0us 0us 104u 261.41u)
SYMBOL res 976 880 R0
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL res 976 800 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage 928 800 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL res 1600 608 R0
SYMATTR InstName R3
SYMATTR Value 12K
SYMBOL res 1600 528 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage 1552 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value .9v
SYMBOL res 1712 848 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R9
SYMATTR Value 12K
SYMBOL res 1712 944 R180
WINDOW 0 38 67 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R11
SYMATTR Value 1k
SYMBOL voltage 1696 912 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value .7v
SYMBOL res 1552 848 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R12
SYMATTR Value 12K
SYMBOL res 1552 928 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R13
SYMATTR Value 1k
SYMBOL voltage 1536 912 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value .6v
SYMBOL res 1440 640 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R14
SYMATTR Value 12K
SYMBOL res 1440 720 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R15
SYMATTR Value 1k
SYMBOL voltage 1488 720 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V10
SYMATTR Value .5
SYMBOL Digital\\dflop 272 432 R0
SYMATTR InstName A2
SYMBOL Digital\\dflop 272 656 R0
SYMATTR InstName A3
SYMBOL Digital\\dflop 272 896 R0
SYMATTR InstName A4
SYMBOL Digital\\and 48 400 R0
SYMATTR InstName A5
SYMBOL Digital\\and 48 480 R0
SYMATTR InstName A6
SYMBOL Digital\\and 48 624 R0
SYMATTR InstName A7
SYMBOL Digital\\and 48 704 R0
SYMATTR InstName A8
SYMBOL Digital\\and 48 896 R0
SYMATTR InstName A9
SYMBOL Digital\\or 128 432 R0
SYMATTR InstName A11
SYMBOL Digital\\or 128 656 R0
SYMATTR InstName A12
SYMBOL Digital\\and -272 560 R0
SYMATTR InstName A15
SYMBOL Digital\\or -352 592 R0
SYMATTR InstName A16
SYMBOL Digital\\or -160 240 R0
SYMATTR InstName A18
SYMBOL Digital\\and 640 176 R0
SYMATTR InstName A13
SYMBOL Digital\\inv 416 160 R0
SYMATTR InstName A20
SYMBOL voltage -480 624 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value PULSE(0 1 12.5u 0 0 5u 20u)
SYMBOL res 1424 912 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage 1408 896 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value .8v
SYMBOL res 1280 832 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 36K
SYMBOL res 1280 752 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 36K
SYMBOL res 1280 928 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 36K
SYMBOL Digital\\inv 256 1024 R0
SYMATTR InstName A21
SYMBOL Digital\\dflop 496 432 R0
SYMATTR InstName A22
SYMBOL Digital\\dflop 496 656 R0
SYMATTR InstName A23
SYMBOL Digital\\dflop 496 896 R0
SYMATTR InstName A24
SYMBOL Digital\\srflop 1568 160 R0
SYMATTR InstName A25
TEXT 520 -40 Left 0 !.tran .02
TEXT 280 -232 Left 0 ;probe thses nodes to get a timing diagram in the scope
TEXT 904 504 Left 0 ;This bumf is for\ngenerating the \nvoltages for the \ntiming diagram
 
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