I see on the Wikipedia
entry for flip-flops that using two of them minimizes the
probability of the problems encountered when the gate signal
happens to come at the same time as a clock signal
(glitches/slivers?).
I guess this iw what Jason Betts was
suggesting, and I will probably try this initially. The shift
register trick is a good one for small bursts. thanks, slim
that's part of what I was saying... my other circut was another
fixed-length one
Right, I want to control the number of pulses per burst by
changing the width of the gate pulse.
I was thinking you might be wanting that!
To do that you need a scale to measure the length of the gate pulse
against, a scale that is finer than the pulses you are trying to gate.
, one way to do this ould be to use a clock that runs faster
than the pulse signal and an up-down counter.
I used a clock that's exactly three times the speed of your pulse clock
and phase locked. - easiest way to get that is to generate both from
the same source, anyway here's the ltspice schematic.
I only count the early part of the gate pulse (the part that arrives
before the first clock pulse is emitted) and then I tack that much
extra time onto the end of the trigger pulse.
It's quite possible that this can be done with fewer parts, I stopped
when it was working in simulation and reasonably tidy looking
Version 4
SHEET 1 2120 1220
WIRE 1344 48 -336 48
WIRE 1456 48 1408 48
WIRE 1952 48 1456 48
WIRE -336 64 -336 48
WIRE 1296 80 848 80
WIRE 1344 80 1296 80
WIRE -336 160 -336 144
WIRE -256 208 -368 208
WIRE 1456 208 1456 48
WIRE 1520 208 1456 208
WIRE -368 224 -368 208
WIRE -256 224 -256 208
WIRE 416 224 -256 224
WIRE 608 224 480 224
WIRE 688 224 672 224
WIRE -64 240 -208 240
WIRE 608 256 544 256
WIRE 1520 256 1456 256
WIRE 1664 256 1632 256
WIRE -208 288 -208 240
WIRE -192 288 -208 288
WIRE -368 304 -384 304
WIRE -256 320 -256 224
WIRE -192 320 -256 320
WIRE -112 320 -128 320
WIRE -64 320 -64 240
WIRE 544 320 544 256
WIRE 544 320 -64 320
WIRE 656 320 544 320
WIRE 688 368 688 224
WIRE 1456 368 1456 256
WIRE 1456 368 688 368
WIRE 1664 400 1664 256
WIRE 1664 400 -64 400
WIRE -256 448 -256 320
WIRE 16 448 -256 448
WIRE 96 448 80 448
WIRE 96 464 96 448
WIRE 1824 464 880 464
WIRE -64 480 -64 400
WIRE 16 480 -64 480
WIRE 192 480 160 480
WIRE 416 480 352 480
WIRE 640 480 576 480
WIRE 848 480 848 80
WIRE 848 480 640 480
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WIRE 16 528 -112 528
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WIRE 192 528 176 528
WIRE 416 528 400 528
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WIRE 656 528 592 528
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WIRE -16 592 -16 560
WIRE 608 592 -16 592
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WIRE 176 608 -240 608
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WIRE -384 640 -432 640
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WIRE -384 672 -416 672
WIRE -16 672 -16 624
WIRE 16 672 -16 672
WIRE 80 688 80 672
WIRE 96 688 80 688
WIRE -64 704 -64 480
WIRE 16 704 -64 704
WIRE 192 704 160 704
WIRE 416 704 352 704
WIRE 608 704 608 592
WIRE 608 704 576 704
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WIRE -64 720 -416 720
WIRE 1616 720 1616 704
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WIRE 16 752 -112 752
WIRE 96 752 80 752
WIRE 176 752 176 608
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WIRE 400 752 400 528
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WIRE 1424 752 1424 704
WIRE 1488 752 1488 704
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WIRE -432 768 -432 640
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WIRE 1408 816 1392 816
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WIRE 640 832 -16 832
WIRE 1536 832 1520 832
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WIRE 1280 848 1264 848
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WIRE 1536 928 1536 912
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WIRE 208 944 192 944
WIRE 416 944 352 944
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WIRE 416 992 400 992
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WIRE 1408 1008 1408 992
WIRE 1696 1008 1696 992
WIRE 1536 1024 1536 1008
WIRE 880 1056 880 464
WIRE 1184 1056 880 1056
WIRE 1824 1056 1824 464
WIRE 1824 1056 1184 1056
WIRE 176 1088 176 992
WIRE 256 1088 176 1088
WIRE 400 1088 400 992
WIRE 400 1088 320 1088
FLAG -336 160 0
FLAG -384 304 0
FLAG 928 896 0
FLAG 1040 896 pulse_clock
FLAG 1552 624 0
FLAG 1664 624 trigger_clock
FLAG 1696 1008 0
FLAG 1680 848 sync_out
FLAG 1536 1024 0
FLAG 1520 832 output
FLAG 1488 624 0
FLAG 1408 624 pulse_clock2
FLAG 352 -192 pulse_clock
FLAG 352 -160 pulse_clock2
FLAG 352 -128 trigger_clock
FLAG 352 -96 ctr_state
FLAG 352 -64 sync_out
FLAG 352 -32 output
FLAG -480 720 0
FLAG 1408 1008 0
FLAG 1392 816 ctr_state
FLAG 1536 752 out
FLAG 1952 48 out
FLAG 1296 80 sync
FLAG 1696 752 sync
FLAG 640 480 ctr1
FLAG 1184 768 ctr1
FLAG 1184 848 ctr2
FLAG 608 704 ctr2
FLAG 640 944 ctr3
FLAG 1184 944 ctr3
FLAG -336 48 Pulses
FLAG 992 976 Pulses
FLAG -256 208 trigger
FLAG 1616 720 trigger
FLAG -480 608 timer
FLAG 1424 528 timer
FLAG 1184 1056 0
SYMBOL voltage -336 48 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V1
SYMATTR Value PULSE(0 1 0 0 0 .00001 .00006)
SYMBOL Digital\\and 1376 0 R0
SYMATTR InstName A1
SYMBOL voltage -368 208 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V2
SYMATTR Value PULSE(0 1 0 0us 0us 104u 261.41u)
SYMBOL res 976 880 R0
SYMATTR InstName R1
SYMATTR Value 12K
SYMBOL res 976 800 R0
SYMATTR InstName R2
SYMATTR Value 1k
SYMBOL voltage 928 800 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V3
SYMATTR Value 1
SYMBOL res 1600 608 R0
SYMATTR InstName R3
SYMATTR Value 12K
SYMBOL res 1600 528 R0
SYMATTR InstName R4
SYMATTR Value 1k
SYMBOL voltage 1552 528 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V4
SYMATTR Value .9v
SYMBOL res 1712 848 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R9
SYMATTR Value 12K
SYMBOL res 1712 944 R180
WINDOW 0 38 67 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R11
SYMATTR Value 1k
SYMBOL voltage 1696 912 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V8
SYMATTR Value .7v
SYMBOL res 1552 848 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R12
SYMATTR Value 12K
SYMBOL res 1552 928 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R13
SYMATTR Value 1k
SYMBOL voltage 1536 912 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V9
SYMATTR Value .6v
SYMBOL res 1440 640 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R14
SYMATTR Value 12K
SYMBOL res 1440 720 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R15
SYMATTR Value 1k
SYMBOL voltage 1488 720 R180
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V10
SYMATTR Value .5
SYMBOL Digital\\dflop 272 432 R0
SYMATTR InstName A2
SYMBOL Digital\\dflop 272 656 R0
SYMATTR InstName A3
SYMBOL Digital\\dflop 272 896 R0
SYMATTR InstName A4
SYMBOL Digital\\and 48 400 R0
SYMATTR InstName A5
SYMBOL Digital\\and 48 480 R0
SYMATTR InstName A6
SYMBOL Digital\\and 48 624 R0
SYMATTR InstName A7
SYMBOL Digital\\and 48 704 R0
SYMATTR InstName A8
SYMBOL Digital\\and 48 896 R0
SYMATTR InstName A9
SYMBOL Digital\\or 128 432 R0
SYMATTR InstName A11
SYMBOL Digital\\or 128 656 R0
SYMATTR InstName A12
SYMBOL Digital\\and -272 560 R0
SYMATTR InstName A15
SYMBOL Digital\\or -352 592 R0
SYMATTR InstName A16
SYMBOL Digital\\or -160 240 R0
SYMATTR InstName A18
SYMBOL Digital\\and 640 176 R0
SYMATTR InstName A13
SYMBOL Digital\\inv 416 160 R0
SYMATTR InstName A20
SYMBOL voltage -480 624 M0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V5
SYMATTR Value PULSE(0 1 12.5u 0 0 5u 20u)
SYMBOL res 1424 912 R180
WINDOW 0 36 76 Left 0
WINDOW 3 36 40 Left 0
SYMATTR InstName R6
SYMATTR Value 1k
SYMBOL voltage 1408 896 R0
WINDOW 123 0 0 Left 0
WINDOW 39 0 0 Left 0
SYMATTR InstName V6
SYMATTR Value .8v
SYMBOL res 1280 832 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R5
SYMATTR Value 36K
SYMBOL res 1280 752 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R7
SYMATTR Value 36K
SYMBOL res 1280 928 R90
WINDOW 0 0 56 VBottom 0
WINDOW 3 32 56 VTop 0
SYMATTR InstName R8
SYMATTR Value 36K
SYMBOL Digital\\inv 256 1024 R0
SYMATTR InstName A21
SYMBOL Digital\\dflop 496 432 R0
SYMATTR InstName A22
SYMBOL Digital\\dflop 496 656 R0
SYMATTR InstName A23
SYMBOL Digital\\dflop 496 896 R0
SYMATTR InstName A24
SYMBOL Digital\\srflop 1568 160 R0
SYMATTR InstName A25
TEXT 520 -40 Left 0 !.tran .02
TEXT 280 -232 Left 0 ;probe thses nodes to get a timing diagram in the scope
TEXT 904 504 Left 0 ;This bumf is for\ngenerating the \nvoltages for the \ntiming diagram