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Ganging H-Bridges

Discussion in 'Electronic Design' started by Jon Slaughter, Apr 7, 2008.

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  1. Is it common to parallel h-bridges?
     
  2. BTW, I can't seem to find any in-expensive H-Bridges for [email protected] so I was
    thinking of using two of these

    http://www.fairchildsemi.com/ds/FD/FDD8424H.pdf


    But I'd like to find a full bridge with some protection in it(current
    limiting, temperature, etc...).

    Any ideas?

    Thanks,
    Jon
     
  3. Guest

    It isn't usually a good idea - the tolerance on the gate threshold
    voltages usually means that one side of the pair carries the bulk of
    the current, and as that device gets hotter its gate threshold voltage
    will drop, leading it to carry even more.
    At currents above 30A the postive temperature coefficient of the
    channel resistance of these parts beats out the negative temperature
    coefficient of the gate source voltage, so if you are looking to
    switch more than 60A you might get away with it.

    Otherwise you'd need to add a small resistance in series with each
    source to force current sharing.
     

  4. I don't see any difference between parallel H-bridges and discretizing the
    H-bridge and paralleling the individual mosfets... which is no problem.
     
  5. Guest

    If you don't think it is a problem, you haven't been doing it for long
    enough or on a large enough scale.

    If you want to parallel MOSFETs or discrete transistors you almost
    always have to add components to make sure that each active device
    carries more or less the same current. Production tolerance is not
    your friend.
     

  6. But this contradicts AOE and many other sources I have read that say
    paralleling them is no problem. MOSFETS have negative temperature
    coefficients rather than positive like BJT's. (hence as one gets hotter it
    gets more resistive and less current will flow through it and through the
    other.. they should ultimately balance out, in proportion, if it is not too
    bad)

    I assume then you mean that one mosfet might take a little more current than
    another because they are not exactly the same. Ok, that might be true but
    then you just add one more mosfet to the mix and it should compensate enough
    (assuming they are not that much different, which I imagine they aren't).

    The only issue it says is that the more you parallelize the more gate cap
    you have hence its harder to drive(and eventually becomes impossible).
    Of course that stuff is for discrete mosfets and I'm not sure about
    h-bridges(specially since they probably have more circuitry in it for other
    things, in general).
     
  7. Guest

    Go back to my original response (the third one in the list) and read
    it to the end. Then take a careful look at the datasheet that you
    posted. MOSFETs only had a positive temperature coefficient for high
    drain currents - higher than you are likely to be using. Check out the
    drain current versus gate-voltage curves in the data sheet you posted,
    rather relying on Win Hill's thirty year-old observation about a much
    smaller MOSFET than you will be using - the 2N4351 data in his figure
    3.13 switches to a positive temperature coefficient at 2mA, which the
    Fairchild part you are contemplating has a negative temperature
    coefficient up to 30A.

    And MOSFETs have fairly large gate threshold voltage tolerances, so
    you are quite likely to start off with all the current going through
    one of your parallelled MOSFETs, which isn't a good start.
    Using your imagination is a poor substitute for reading the data sheet
    carefully
    It never becomes impossible - the switching times just grow in direct
    poroportion to the number of MOSFET's.
    Dream on. If they do incorporate current limiting or thermal
    protection, the data sheet will tell you about it, and you won't want
    either to come into action in normal operation.
     
  8. Guest

    Diplomatic, but wrong.
    Good advice, but it doesn't help current sharing, for which you need a
    source resistor per part if you aren't operating at high enough
    currents for the positve temperature coefficient of the channel
    resistance to swamp the negative temperature coefficient of the gate
    threshold voltage.
     
  9. Go back to my original response (the third one in the list) and read
    it to the end. Then take a careful look at the datasheet that you
    posted. MOSFETs only had a positive temperature coefficient for high
    drain currents - higher than you are likely to be using. Check out the
    drain current versus gate-voltage curves in the data sheet you posted,
    rather relying on Win Hill's thirty year-old observation about a much
    smaller MOSFET than you will be using - the 2N4351 data in his figure
    3.13 switches to a positive temperature coefficient at 2mA, which the
    Fairchild part you are contemplating has a negative temperature
    coefficient up to 30A.

    And MOSFETs have fairly large gate threshold voltage tolerances, so
    you are quite likely to start off with all the current going through
    one of your parallelled MOSFETs, which isn't a good start.
    Using your imagination is a poor substitute for reading the data sheet
    carefully
    It never becomes impossible - the switching times just grow in direct
    poroportion to the number of MOSFET's.
    Dream on. If they do incorporate current limiting or thermal
    protection, the data sheet will tell you about it, and you won't want
    either to come into action in normal operation.

    --------

    I suggest you read

    http://www.irf.com/technical-info/appnotes/para.pdf

    because you seem to think MOSFETS = BJT's.
     
  10. I suggest you read
    for example,

    "Differential RDS (on) will cause current unbalance and extra conduction
    losses as expected, but these are limited due to the

    positive temperature coefficient for MOSFET resistance. The thermal
    'runaway' characteristic of other semiconductor technologies

    does not apply to MOSFETs."



    "Gain factor differentials (DGF) result in limited current unbalance. In the
    extreme, which is difficult to realize in practice,

    the current unbalance is limited to the gain ratio. Since turn-on
    differentials are very easy to control, the predominate loss

    differential occurs during turn-off."



    And the pdf just about contradicts everything you have said so far. (except
    maybe in the rare case where there is a complete parameter mismatch). Of
    course its not only the pdf but other sources too.
     
  11. Guest

    Current differentials during turn-on and turn-off do depend on the
    differences between the device gate-threshold voltages. For the
    Fairchild parts you nominated, the worst case limits are 1V and 3V. A
    1V part would be carrying about 50A before a 3V part started to turn
    on. Paralleling two transistors with that level of mismatch would put
    almost all the switching disipation in the lower threshold part.

    Forsythe weasels around this point - his job is selling MOSFETs - but
    it's in his paper, if you read it carefully.
     
  12. Guest

    I suspect that neither Terry nor Jon has thought about the increased
    dissipation in MOSFET switches during switching. My 1996 Peltier
    junction thermostat paper talked about setting the switching frequency
    for the PWM output stage at around 200kHz to get roughly equal static
    and dynamic power dissipiations in our switching MOSFETs - more recent
    circuits switch appreciably faster and this dissipation would
    presumably be dominant in these applications.
     
  13. Guest

    Don't guess. Dig out a calcular or dig into LTSpice and work out what
    would actually happen.

    People are good at ignoring issues they don't want to think about, or
    aren't important in the area of their immediate interest. For the
    Fairchild FDD8424H that you were thinking about using, the 1V to 3V
    range tolerance on the gate threshold voltage - if manifested between
    two parallelled switching transistors - would have the lower threshold
    transistor carrying some 50A more of the switching current than its
    high threshold partner.

    How much extra switching dissipation this would generate in the lower
    threshold part depends on the complex impedance of the load being
    switched, but it could well be that the lower threshold part would be
    doing all the heavy switching.
     
  14. Guest

    Don't be silly.

    If you are using the devices purely as switches, the situation does
    get more complicated.

    The static current distribution is then determined entirely by the
    "on" channel resistance, and while - as Forsythe says - you still have
    to take into account the worst case tolerance range in the on channel
    resistance, at least you can rely on a positive temperature
    coefficient to avoid a bad distribution getting worse.

    The data sheet for the Fairchild parts you nominated doesn't specify a
    worst case minimum "on" resistance;
    the typical to worst case maximum ratio is close to 3:4 so one might
    hope for a minimum to maximum ratio of 2:1 which isn't too good.

    The dynamic current distribution - while the switches are turning on
    and off - does depend on the gate threshold vvoltage, with most of the
    current concentrating on the part with the lowest threshold voltage
    when the devices turn on and turn off. The switches don't spend all
    that long a time switching on and off, but a lot of power gets
    dissipated in the junctions while this is going on - I used to select
    switching frequencies such that the static and dynamic power
    dissipations in the switches were more or less the same, but if I'd
    been under pressure to minimise the size and cost of the components
    doing the output filtering I'd have probably set the swithing
    frequencies rather higher.
     
  15. I have no idea but I have read about 10 sources, one such as AOE, that says
    they can easily be paralleled and say nothing else about "issues" that bill
    is talking about. Of course if you just take two random mosfets(such as a
    power and a small signal) and throw them together then it probably won't
    work... but that pdf says in general there are no issues and only when the
    parameters are significantly mismatched will there be an issue.

    My guess is he really think's MOSFET's are BJT's cause everything he is
    talking about pretty much applies to BJT's but not MOSFET's.
     
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