hi, can some one tell me what this GAL16V8D pal chip actually does ? in a
simple way........?
A GAL is a programmable logic circuit. Several (N)ANDs (N=ORs can be
simply replaced by one single circuit, saving place, supply current,
and, additionally, it makes it more flexible.
I have used a GAL16V8 for address decoding logic in a single board
system:
-----------------
ROM RAM LCD DIN1 DIN2 DOUT1 DOUT2
/AHH X x 1 1 1 1 1
/AHL X x 1 1 1 1 1
/PSEN 0 1 1 1 1 1 1
A7 A A 1 1 1 1 1
A6 A A 1 1 1 1 1
A5 A A 1 1 1 1 1
A4 A A 1 1 1 1 1
A3 A A 0 1 0 1 0
A2 A A 0 0 1 0 1
/RD 0 X X 0 0 x x
/WR X X X X x 0 0
Resulting
Range From 0x0000 0x0000 0xFFF0 0xFFF8 0xFFF4 0xFFF8 0xFFF4
To 0xFFFF 07FEF 0xFFF3 0xFFFC 0xFFF7 0xFFFC 0xFFF7
-----------------
This follows to a boolean algebra like this:
-----------------
lcden = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /wr +
psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /rd
/din1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /rd
dout1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /wr
/din2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /rd
dout2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /wr
/csrom = /psen * /rd
/csram = psen * /rd * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2 +
psen * /wr * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2
-----------------
Finally the programming of these ANDs and ORs can be made with a text
editor, a GAL ASM compiler translating the logic needs into a
programmable file. Finally u put this file with a GAL programmer into
the circuit.
title ADDRESS DECODER V2
pattern MOGAv10a
revision A
author Heinz Liebhart
company private
date 05/01/1999
chip MOGAv10a GAL16V8
;pin 1 2 3 4 5 6 7
8 9 10
; IN IN IN IN IN IN IN
IN IN SUPPLY
ahh ahl a7 a6 a5 a4 a3
a2 rd gnd
;pin 11 12 13 14 15 16 17
18 19 20
; IN IN OUT OUT OUT OUT OUT
OUT OUT SUPPLY
psen wr lcden din1 din2 dout1 dout2
csram csrom vcc
equations
lcden = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /wr +
psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * /a2 * /rd
/din1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /rd
dout1 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * /a2 * /wr
/din2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /rd
dout2 = psen * /ahh * /ahl * a7 * a6 * a5 * a4 * /a3 * a2 * /wr
/csrom = /psen * /rd
/csram = psen * /rd * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2 +
psen * /wr * /ahh * /ahl * a7 * a6 * a5 * a4 * a3 * a2
-----------------
Aaah, we already know this equations ;-)
The GAL ASM "compiler" is producing a jedec file for programming the
chip and a log file, which e.g. looks like that:
-----------------
EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991
Document file for MOGAv10a.eqn
Device: 16V8
$LABELS 20 ahh ahl a7 a6 a5 a4 a3 a2 rd gnd psen wr lcden din1 din2
dout1 dout2 csram csrom vcc
Pin Label Type
--- ----- ----
1 ahh com input
2 ahl com input
3 a7 com input
4 a6 com input
5 a5 com input
6 a4 com input
7 a3 com input
8 a2 com input
9 rd com input
10 gnd ground pin
11 psen com input
12 wr com input
13 lcden pos,com output
14 din1 neg,com output
15 din2 neg,com output
16 dout1 pos,com output
17 dout2 pos,com output
18 csram neg,com output
19 csrom neg,com output
20 vcc power pin
EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991
Device Utilization:
No of dedicated inputs used : 10/10 (100.0%)
No of feedbacks used as dedicated inputs : 1/6 (16.7%)
No of dedicated outputs used : 2/2 (100.0%)
No of feedbacks used as dedicated outputs : 5/6 (83.3%)
------------------------------------------
Pin Label Terms Usage
------------------------------------------
19 csrom 1/8 (12.5%)
18 csram 2/8 (25.0%)
17 dout2 1/8 (12.5%)
16 dout1 1/8 (12.5%)
15 din2 1/8 (12.5%)
14 din1 1/8 (12.5%)
13 lcden 2/8 (25.0%)
------------------------------------------
Total 9/64 (14.1%)
------------------------------------------
EQN2JED - Boolean Equations to JEDEC file assembler (Version V003)
Copyright (R) National Semiconductor Corporation 1990,1991
Chip diagram (DIP)
._____ _____.
| \__/ |
ahh | 1 20 | vcc
ahl | 2 19 | csrom
a7 | 3 18 | csram
a6 | 4 17 | dout2
a5 | 5 16 | dout1
a4 | 6 15 | din2
a3 | 7 14 | din1
a2 | 8 13 | lcden
rd | 9 12 | wr
gnd | 10 11 | psen
|______________|
-----------------
Finally this means for your (reverse) engineering:
- Find out which pins are input, which are output.
- Check which in combinations can occur.
- Check the out values for these in.
Then you can do your reverse engineering.
A simple binary counter connected to the inpus might be useful ;-)
Hope this helps,
Heinz