Connect with us

Frequency Divider

Discussion in 'General Electronics Discussion' started by Virium, Jun 27, 2016.

Scroll to continue with content
  1. Virium


    Jun 27, 2016
    Hello everybody, asking for some help with a frequency divider using a D flip flop.
    The chip on the left is a D flip flop, I feed a signal (f) in to the clock and it outputs it to me halved (f2), it works fine.
    I am trying to simulate the same using logic gates, and getting no results.
    The output is nothing I desire, the pulses are about 25x faster and the clock signal turns into DC.
    What am I doing wrong here ?
    Thank you for your time

    Attached Files:

  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

    Jan 21, 2010
    the problem is that your gate version passes D to Q while the clock is high. The other one does it as the clock goes high.

    the practice upshot is that your gate version is not limited to a single transition during each clock cycle
  3. Harald Kapp

    Harald Kapp Moderator Moderator

    Nov 17, 2011
    To avoid this, look up master-slave flip flop.
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day