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Frequency Divide by 2.5?

Discussion in 'Electronic Design' started by Jackson Harvey, Oct 31, 2003.

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  1. I ran into a divide by 1.5 circuit that uses a positive-edge triggered
    flip-flop and a negative-edge triggered flip-flop. I like the concept,
    but I need to divide by 2.5. Has anyone seen such a circuit, or have
    any idea how to go about designing it?

    Divide by 1.5 is at:

    http://www.designnotes.com/CIRCUITS/divide3_2.htm

    Thanks,
    Jackson Harvey
     
  2. mike

    mike Guest

    divide by 5 then use an edge detector to double it.
    mike

    --
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  3. red rover

    red rover Guest

    Or if you like, use a x5 PLL and use a flip-flop to
    halve it.

    Steve
     
  4. Jim Thompson

    Jim Thompson Guest

    See "DivideBy2p5.pdf" on the S.E.D/Schematics page of my website.

    I am in no way a digital designer... there may be a more compact
    realization. Probably someone here who knows VHDL can concoct such a
    version.

    ...Jim Thompson
     
  5. Robert Baer

    Robert Baer Guest

    If one multiplies by five, then divides by two, that is a
    multiplication of 2.5 - not a divide by 2.5 ....
     
  6. You need to divide by five and multiply by two. Simplest method that will
    also produce a symmetrical output.

    Cheers!

    Chip Shults
    My robotics, space and CGI web page - http://home.cfl.rr.com/aichip
     
  7. Jim Thompson wrote...
    I designed a divide-by-2.5 that uses three flip flops (instead of
    four like Jim's). If one wants a symmetrical output it uses a four
    quad NOR-gates. It doesn't require two types of gates (e.g. like
    Jim's Exclusive-OR and AND gates). Although it uses three logic
    packages, it has one left-over flip flop. If an asymmetric output
    is acceptable, two gates also remain unused. Like Jim, I suspect
    a more simple implementation may be possible.

    Thanks,
    - Win

    whill_at_picovolt-dot-com
     
  8. Fred Bloggs

    Fred Bloggs Guest

    There is a simple way to divide by N/2 for any odd N- all these circuits
    stink from a phase noise perspective. You're not a hardware person and
    that shows- stick with your programming and post your trivia to basics
    from now on- you're deluded to think your joke of a question flies here.
     
  9. Jim Thompson

    Jim Thompson Guest

    Can we see your schematic?

    ...Jim Thompson
     
  10. Jim Thompson

    Jim Thompson Guest

    Whatsa matta Fred, spend all Friday night drinking ?:) You sure are
    a cranky old bastard!

    ...Jim Thompson
     
  11. Jim Thompson

    Jim Thompson Guest

    Eh? It just struck me what you said, "If one wants a symmetrical
    output it uses a four quad NOR-gates".

    SYMMETRICAL? How are you doing that with DIV 2.5 ?? That would take
    a transition at quarter-cycle of the input clock.

    ...Jim Thompson
     
  12. Joe Legris

    Joe Legris Guest

    Hey Bloggs, you've been quite civil for some time, but now you're
    changing into Mr. Hyde again. What's happening?
     
  13. Look at:

    http://www.xilinx.com/xcell/xl33/xl33_30.pdf

    I can imagine other designs as well. For example you can multiply the clock
    by two, using a quad exclusive or (7486) to produce a short pulse on every
    clock edge and then divide this by five using a 7490.

    petrus
     
  14. Jim Thompson

    Jim Thompson Guest

    [snip]

    Clock ×2 is what I did using the '74 plus an XOR.

    ...Jim Thompson
     
  15. The concept for integer dividers is to count only the transitions that
    go in one direction. The concept for half integer dividers is to
    count all the transitions. So a divide by 2.5 is a divide by 5
    counter that counts all transitions. However, if the original
    waveform is not symmetrical, then there will be a bit of asymmetry in
    the output wave, if that matters.
     
  16. gwhite

    gwhite Guest

    It isn't "noise."
     
  17. Jim Thompson

    Jim Thompson Guest

    Fred is referring to the noise problems when used in a PLL.

    ...Jim Thompson
     
  18. gwhite

    gwhite Guest


    Please elaborate. Like Popelish wrote "However, if the
    original waveform is not symmetrical, then there will be
    a bit of asymmetry in the output wave, if that matters."

    That would create a deterministic spurious output if applied directly to a PD
    (like primitive fractional PLL's that don't "randomly" insert the extra
    clocks). But deterministic is by definition not random. Noise is by definition
    random. What inherent feature of these circuits creates a "high amount" of
    randomness? Why would anyone apply the output of this circuit directly to a PD?
     
  19. Jim Thompson

    Jim Thompson Guest

    I didn't say Fred was right ;-)

    If you feed the result of the DIV2p5 into a single edge sensitive PD
    there would be no problem.

    ...Jim Thompson
     
  20. I am not sure if this was directed at me, since the reply does not seem
    to fit my question. Just in case, though: I am a hardware designer, but
    not a digital designer. You seem to have made some assumptions that are
    not warranted. I do not care about duty cycle, and I do not care about
    phase noise. What I actually need is a divide by 5 with approximately
    50% duty cycle, and I know that the input duty cycle is nearly 50%. I
    will follow it up with a divide by 2 to give me approximately 50% duty
    cycle, and approximately is good enough for my application.

    BTW, I have found many ways to solve the problem, but am working on
    generating the minimum hardware solution. Thanks to those who replied
    constructively. In case anyone cares, I wrote a program to search the
    entire state-transition-table search space, and applied the appropriate
    rules to find just those transition tables that lead to a divide by
    2.5. It was a fun exercise, but I was left with many answers, so now I
    am writing a rule to select the minimum hardware solution.

    Thanks,
    Jackson Harvey
     
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