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FPGA/CPLD VGA Generator and Shared Memory Access

Discussion in 'Electronic Design' started by Krystian Sergiejew, Aug 10, 2003.

  1. I am thinking about designing a single board computer that would be capable
    of generating VGA signals to display images stored in SRAM on the monitor.
    The VGA generator would be implemented in CPLD or FPGA, and it would share
    the memory with the processor. Basically, somewhere in the CPU's address
    space, I would have a location where the screen image would be stored. The
    idea is that the screen image would be accessible by both, the CPU and the
    FPGA. The FPGA generator would constantly read from memory the pixel values
    and display them on the monitor. However, the CPU should also have the
    read/write access to the screen image so that it could be modified.

    How do I implement all that so that everything works and doesn't collide?
    How do I prevent the CPU and FPGA from accessing the memory at the same
    time?

    Any comments/feedback would be highly appreciated.

    Krystian
     
  2. Nico Coesel

    Nico Coesel Guest

    Simple: use the WAIT pin on the CPU to halt the CPU when the VGA
    generator accesses the memory. There is one pitfall though: it is
    possibble that the CPU is accessing the memory when the VGA generator
    needs it. To overcome this, fetch the next byte from the video memory
    right after you have pit a pixel on the screen. In this way you'll
    have the time for one pixel period to fetch the data.
     
  3. Simple: use the WAIT pin on the CPU to halt the CPU when the VGA
    Wouldn't this slow down my CPU a lot? The screen needs to be drawn
    constantly with a 25 MHz pixel clock, but my CPU (65816) will be running at
    10-14 MHz. Would VGA generator have to fetch more than just a byte at the
    time?

    Krystian
     
  4. A E

    A E Guest

    How about using the two phase clock design of the VIC-20?
     
  5. You could use dual-ported ram and then you do not have to worry about
    Thanks! This is exactly the answer I needed. I am just a beginner, so I
    didn't know about the possibility of using dual-ported RAM. Now I just need
    to read up on that.
    I have no idea how you arrived at that or what you mean. But, as about the
    25 MHz clock, I was referring to the dot clock used in driving the display
    timing. 25.1750 MHz is what standard VGA uses to create a 640 x 480 picture.

    Regards,
    Krystian
     
  6. Nico Coesel

    Nico Coesel Guest

    25Hz is probably not going to work on a VGA monitor. You'll need at
    least 800x600 at 60Hz non interlaced.
     
  7. Nico Coesel

    Nico Coesel Guest

    But it is terribly expensive and hard to find. It makes more sense to
    have a memory bank for your software & data and a shared memory bank
    for the VGA adapter. In this way the CPU will only slow down when the
    VGA memory is accessed. You'll need to implement 2 memory banks.
     
  8. I am thinking about designing a single board computer that would be
    capable

    Take a look at www.opencores.org. There you'll find a couple of VGA/CRT
    controller cores for FPGA (one of them is mine).

    My solution for the collision problem was that I used a separate RAM memory
    for Video display. This memory of course could be accessed by the CPU also,
    but was on a separate bus, controlled by the FPGA. This way I had control
    over the arbitration and I could generate wait signals to the CPU when
    needed. I also used a FIFO buffer between the video memory reader part and
    the video clock/sync/signal generation part. This way I didn't have to give
    absolute priority for the video core over the memory. The emptiness of the
    FIFO controlled the priority: when it was almost full, the CPU had higher
    priority, when almost empty, the video core. Now, if you plan to control VGA
    displays and in low resolution (below 640x400) you should count on
    dual-trace. In this mode the controller repeats every row two times for the
    monitor so you physically see more rows on the screen. This is done to
    achieve higher contrast.

    Another option you might have is to get a highly integrated video/CRT
    controller from Epson, the S1D13806. This even has integrated video memory
    so it would give you a single-chip solution.

    regards,
    Andras Tantos
     
  9. Another option you might have is to get a highly integrated video/CRT
    Thanks for the info. I might even try the S1D13806 to keep things simple. I
    just need to read up on that.

    Krystian
     
  10. db

    db Guest

    Who distributes the S1D13806 or other Epson chips in small quantities.
    In particular I am looking for the S1D13A03. I have checked Digikey,
    Arrow and others with no success.
     
  11. Good question, and I would like to know the answer myself too. All I could
    find was Future:

    Item min. quantity unit price
    -----------------------------------------------
    S1D13806F00A100 40 TRAY 33.29

    I know a source in Hungary though ;-)...

    I haven't seen any references to the part you're interested in.
    BTW: a good availability search engine:

    http://www.findchips.com/avail

    Regards,
    Andras Tantos
     
  12. db

    db Guest

    Thanks for the findchips url. I have bookmarked that one.
     
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