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FPGA board design with 2 MIPI CSI-2 camera modules at 4k 60FPS

Discussion in 'Datasheets, Manuals and Component Identification' started by sijafae, May 4, 2021.

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  1. sijafae

    sijafae

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    May 4, 2021
    Hello,

    I am trying to design an FPGA board that has 2 MIPI cameras on it with 4 data lanes each providing a 4k resolution and 60 FPS data stream to a computer. I am thinking of using a Lattice ECP5 for the FPGA board, but it seems as if its MIPI CSI-2 receiver can only do a max 900 Mbps data transfer per lane, while I need about 1.2 Gbps (assuming RAW8). I see that the Lattice's Crosslink can go up to 1.5 Gbps per lane, but this FPGA only got about 5k LUTs. The reason the size of Crosslink is a problem is that I want the FPGA to do some image processing before being sent as a live data stream to the computer.

    I have seen e.g. the Embedded Vision Development Board that uses both a Crosslink and ECP5 separated on 2 different boards: 1 to receive the data stream from the cameras (Crosslink) and merges the 2 video streams, and the other for processing the video stream (ECP5). However, I am not sure what interface they are using between these two FPGAs (MIPI CSI-2 I believe?).

    Thus, my question is... Is it possible to receive the camera video stream with the crosslink, and convert it to a form that can be sent to ECP5, such that 1.2 Gbps transfer per lane (4.8 Gbps per video stream) is possible from Crosslink to ECP5 instead of the 900 Mbps that is the limit on the ECP5's MIPI CSI-2 receiver?
     
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