# Formula for minimum drive current for mosfet

Discussion in 'Electronic Design' started by [email protected], Apr 10, 2008.

1. ### Guest

Check out the data sheet. Figure 7 shows the typical gate charge
required to get the gate voltage up to a level where the part is
turned on - something like 10nC. The worst case total gate charge
listed earlier in the data sheet is 24uC.

20mA s going to take 1.2usec to deliver that 24uC of charge - this is
slow switching by MOSFET standards, and you won't want to switch that
slowly very often, because if you do there is a real risk that the
switch will overheat.

3. ### Jon SlaughterGuest

Why is slower going to going to cause it to heat up? Its less current so
less heat (same amount of charge). In fact it probably would be better
because its spread out over time. (like, say, charging a battery at 1A for 1
year compared to 365A in one day. Same amount of charge but totally diffrent
results)

My switching is at most 100khz(its for motor control so anything about 20khz
should be ok but I'm going for about 50khz). I figure I need about 5 to 10
times this but really it shouldn't be that important(don't need it to be
exact).

Really though, Can you explain to me why a slower switching speed will cause
it to heat up more? It contradict's everything I know about transister
switches and switching speed.

4. ### Paul E. SchoenGuest

The uC is not what will heat up, although at 100 kHz it could get a little
warm. But the MOSFET will dissipate power during the time it is in its
linear region during switching, and if you are controlling something like
12V and 6A, you can have as much as 18 watts during this time. At 100 kHz,
you could have 1 uSec of high power dissipation on each transition, every 5
uSec, or 20% duty cycle, and about 3.6 watts of switching losses (as a
rough estimate).

I had problems driving an FQP24N08 at 100 kHz with the on-board 1 amp gate
driver of a UC1843a, such that I was barely getting 75% efficiency with a
12 V input at 40 watts output. It also has about 25 nC maximum gate charge.
I was also losing about 1.2 watts in conduction losses with 0.05 ohms
RdsOn. So I used a 6 amp gate driver UC3710, with an HUF75645 MOSFET, and I
got close to 90% efficiency. This MOSFET has up to 238 uC gate charge, but
its RdsOn is only 0.016 ohms, so I had less conduction loss. The driver
gets a bit warm, too, so this is probably not an optimal combination. Just
charging and discharging the 3800 pF gate capacitance takes a fair amount
of power, probably about half a watt.

Paul

5. ### Guest

The maximum heat dissipation during switching occurs when the voltage
across the switch is half way between the rails. The longer the time
the drain takes to get from one rail to the other, the longer this
dissipation keeps on happening.

Spice can work it out for you if you model your load tolerably
accurately
It ain't what you don't know that screws you up, but what you think
you know that ain't so.

You need to develop a better understanding of what is going on while
the current through the switch moves from off to full on, and the
voltage across the switch moves from the full rail voltage to
practically nothing.

In the middle of this process the instantaneous power dissipation in
the swtich gets pretty high - you can work out exactly how high - and
since the process takes a finite time - 10 to 20nsec if you know what
you are doing, a microsecond or so if you cheapskate on the driver -
each switching opertion dumps a predictable amount of energy into the
switch junction.

Work it out.

6. ### Guest

I believe what these posters are trying to say is that independent of
the frequency of operation, you want to switch the fet quickly to stay
out of the linear region. It is not the frequency, but rather the
"squareness" of the driving voltage that is of concern. In addition,
the posters were concerned with the "shoot through" or crowbar
current, which can be avoided with a break before make circuit.

The equation you were trying to think is the one for the average
current used in driving a gate. You can probably derive it.
I = dQ/dt , but in a "macro sense" we have a packet of charge Q
transfered over a period T.
Q=CV where C is the gate capacitance and V is the peak drive voltage
1/dt is really the switching frequency F

I = CVF.

7. ### Jon SlaughterGuest

I think you need to work it out. You don't seem to have any clue what your

You might be right in that the maxmimum instantanous power dissipated in
charging the capacitances is when V is half way min and max but what you
fail to realize is that this is independent on frequency. (I might linger
around Vpp/2 longer when switching slower but thats only if you take into
account a single switch)

I don't give a crap about what happens instantanous but average. Sure
switching slower might mean that I'm at Vpp/2 longer but on average its the
same if I switch as a frequency twice as fast. Why? Doubt you even read this
but your at the Vpp/2 twice as many times... so it doesn't matter how fast
you switch w.r.t to this power dissipation. Although you end up dissipating
more power for other reasons when you switch faster.

So, point being, If I switch at 2x the frequency I might only be at Vpp/2
half as long but it occurs twice as often and hence cancels. THIS means that
it doesn't matter which frequency I switch at and your logic of "Switching
slower cause more power dissipation" is simply wrong.

In fact almost every site I have seen gives a formula where the power
dissipation is proportional to F and not inverse as you have said.

Jon, the problem is the amount of time it takes the mosfet(s) to
transition from on to off and back from off to on again. During each
switching action of a mosfet it acts like a resistor for the
duration. Heat! So you want the duration of each switching event as
short as possible, regardless of whether these events occur at 100Hz
or 100kHz.
But that's only part of the problem. Fred brings up a good point
Now, when your drive has the gates pulled all the way to the rail
(either one), that's no problem.
But it IS a problem during the switching transition, because both
mosfets are partly turned on providing a path -- not through the load,
but directly across the power rails. You don't want slow switching
here.
So a weak drive is bad.
For motor drive, a kilohertz is probably way plenty, and this lower
frequency is better so that you don't put your mosfets in the hot seat
so often.

9. ### Jon SlaughterGuest

Ok guys, it seems we are talking about two different "Frequencies" here. One
is the speed at which a transition occurs and the other is the number of
times those transitions occur per second. The first really isn't a frequency
since a frequency deals with something that is periodic(or at least that
tends to be the way people think about frequencies).

I do realize that the faster the transition the less power dissipation. That
is pretty basic. And this is independent of frequency(up to a point).

But even having this then the frequency, F, the # of transitions / second,
will increase the power dissipation because we are simply transitioning more
times per second.

So what confused me was when you guys called the frequency of the transition
and I thought it was the frequency of the # of transitions per second. (or
maybe I added that to it or just confused the two).

So we are both right Its true that if you increase the transition speed
that the power dissipation goes down, but if you increase the # of
transitions/per second then the power dissipation goes up.

Hopefully its obvious now...

10. ### Jon SlaughterGuest

BTW, this should point to an optimal switching frequency for least power
dissipation? Anyone know the formula?

11. ### Jon SlaughterGuest

Its not so simple. I do see that now as I stated in the last post I made. I
thought when they said frequency they meant something else and not the
switchign time. (although you do make it much clearer than they did)

But I cannot switch at any frequency and have as fast a transition as I
want. I must drive the gates of the mosfet with BJT's and, of course, they
have there own limits.

Yes, I know.. its basically just like CMOS(I guess it is CMOS) and there is
a short between tranistions.

But there are a few solutions. One is to switch the mosfets on sequentially
instead of at the same time. Al I loose is a bit of power to the motor
momentarily but inertia should smooth it out. (basically delay the PWM a bit
until the transition of the first fet is finished)

But you do make a good point. The problem is, I do have limitations. I do
see bill's point now about using a uC to drive the fets as its probably just
way to low. Ultimately I'd like a formula for drive. (is it a simple RC
circuit(Approximately) or more?)

Well, I do understand that(and its more clear now that you said it). The
thing about that slow of a frequency, from what I've read, is that its
audiable(Which may or may not be an issue depending on how loud it is).

Basically I need to maximize transition time and minimize frequency given
all the contraints. (> 20khz(probably), surge current by drivers(bjt's),
least power dissipation(Although I guess as long as its below max I'm ok)).

Ok, I guess I see the confusion. The subject is minimum drive current for
mosfets. I guess this is bad. I shouldn't require a minimum but a maxium
within the mosfet drivers specs. (basically what I wanted was a formula to
see the relationship)

What I plan on doing is use bjt's to drive the gates in emitter follower...
but I need to configure them for optimal conditions. (max drive current but
within device specs)

Anyways, thanks for the post. Its more clear now but I need to let it settle
in. (I "knew" all the concepts before but there was just no glue tieing them
together ;/)

(Although I'd still like to drive them with the uC if possible because that
is the simplest method... sure it might not be most efficient but if I'm
still able to get reasonble power dissipation then its not *wrong* but just
not optimal)

Thanks,
Jon

12. ### Jon SlaughterGuest

Basically what I'm saying is, is that my drive can supply a surge current of
X, I need to know how much power dissipation this gives. I know ultimately
I'd want to supply as much as possible but, for example, I can't supply 15A
because it has to go through the bjt and then I'll have to worry about power
dissipation in that. (I also don't want to run the BJT's at max to get that
current)

I suppose I could use some other mosfets to drive the gates but seems like
eventually I'll have diminishing returns?

13. ### Guest

The less frequently you switch your transistors, the less energy gets
dumped into them, so you minimise switching losses by not switching.
You don't need a formula to know that.

There isn't much point in getting the power being lost in switching
the transistors (dynamic losses) much below the power being dissipated
in the transistors all the time there is current flowing through them
(static losses).

You've still got to heat sink the transistors well enough to get rid
of the heat generated by the static losses, so you may well choose to
have enough switching events per second so that your dynamic losses
are about the same as your static losses. This makes for smaller and
cheaper inductors and capacitors in your output filter than you'd need
with fewer switching events. As you push the switching frequency
higher you have to balance the need for bigger heat-sinks on your
switches against further reductions in the size of the inductors and
capacitors in the output filter.

14. ### Guest

There is a point where the transistor no longer sees average power but
peak power. Never having designed in a power fet process, I don't know
the design rule. In more general purpose semiconductor processes, the
electromigration frequency limit is 1Khz. That is, a line that is
being pulsed that you wish to consider receiving average current
should be switching faster that 1KHz.

Power MOSFETs do have SOA limits, but it is not as critical as with
bipolars.

I like how you worry about everything. No, really. ;-) There is noting
worse than getting product returned.

If your intent is to drive directly from the uP, you may want to
consider how the load switching will effect the uP. You will probably
get ground bounce. In addition, as you increase VGS, there will be
current flow from CDG. If the drain voltage is falling like a rock, it
to here is you should probably buffer the uP from the power fet.

15. ### Paul E. SchoenGuest

I just finished looking into various MOSFET gate drivers for my design.
They generally cost less than a dollar, and they really switch capacitive
loads quickly, which cuts the switching losses quite a bit. Some good
drivers from National, Maxim, TI, and Microchip are:

TPS2819
LM5112
MCP1415
MAX5048
TC1413
TC4421
UCC27321/2
UC3710

I also played around with a homebrew MOSFET driver using an NPN and PNP
transistor, and a few resistors and diodes, and it seemed to work pretty
well in the simulator. I also set it up with a bootstrap to the MOSFET
drain, with the idea that maybe a driver could be built into a MOSFET, but
it's probably better to tie the voltage supply for the driver to a 5 volt
or 12 volt supply. So you can omit some of this circuitry, but it is
probably a good idea to have some sort of limiting resistor. I tried a
simpler driver with an NPN and PNP with bases tied together as the input
and emitters tied together as the output, with collectors across a 12 volt
supply, and somehow there was simultaneous conduction and one of the
transistors popped. Probably because they were not well matched. So here's
a circuit you can try:

Paul

====================================================================================

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TEXT -304 464 Left 0 !.tran 0 1m 0 startup

Did you use a resistors in each base, or just tie them together?

17. ### Paul E. SchoenGuest

Did you use a resistors in each base, or just tie them together?

I just tied them together. It's basically two emitter followers. They
should never be both on at the same time, but if one is slower than the
other, I guess it can happen, and did. The simulation looked OK.

Paul

I haven't tried to use that totem pole myself, but I remember reading
a comment somewhere by somebody that used two such totem poles in an H-
bridge setup to drive a motor and said he had to use base resistors to
avoid problems. The writer evinced some mystification as to why it
should be so, but empirics rule!
Fred is correct that in principle, you can't bias both transistors on
simultaneously in that topology. Something else happened. Perhaps the
transistors oscillated, and some parasitic effect may made it even
worse. Base resistors would damp that.
I think a little capacitance between base and collector will help tame
high-strung behaviour as well.

As for the question of what frequency to use, you don't need a
formula. You have set a minimum of 20 kHz because it would make noise
below that. Going higher will just dissipate more power, so use
20kHz.

If you find the uC is not enough and you have to use a driver chip,
consider using a "high-low" or "half bridge" driver for two n-channel
devices instead of the fairchild dual p and n. There are lots of such
drivers available, and many incorporate deadtime to prevent cross-
conduction. The only such chip I ever used was the IR2153, but you
should look for the best one for your application.
Besides avoiding the cross-conduction thing, you'll get more bang for
the buck from n-channel mosfets.
Here are a couple of links to those drivers.

http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=2556632

http://search.digikey.com/scripts/DkSearch/dksus.dll?Cat=2556427

20. ### Paul E. SchoenGuest

[snip LTspice]

This developed from my problems with a fairly simple boost converter using
a UC1843a driving a fairly large MOSFET. The FQP24N08 I originally used
seemed to get too hot, and I thought it might be the 0.06 ohm RdsOn, so I
used a beast MOSFET HUF75645 with 0.014 ohms. It drew more primary current
and got hotter, so I assumed it was slow transition of drive voltage
because of the 3800 pF gate capacitance, so I added a driver, and that
seemed to fix it. Then I tried some ideas for a simple gate driver, and it
became not so simple.

But the LTspice simulations did not show that much higher dissipation with
fairly slow transitions (up to about 1 uSec), which I was simulating with
high values of series resistance and gate capacitance. I don't have exact
models of the two transistors I used. I'm still a bit stumped as to why the
UC1843a doesn't work well enough for the FQP24N08.

I tried the simple NPN/PNP emitter follower gate driver because it seemed
to work OK in LTspice, and it would be cheap and simple to add to the
circuit. But the simulation was with 2N3904 and 2N3906, while I used an
MPSA06 and an MJE170 (which I have lots of). The drive signal was directly
from the gate driver of the UC1843a, which has a rise/fall time of 50 nSec
into 1000 pF, and probably 10 nSec into just the bases, so it was probably
fast enough to cause cross-conduction, especially with the mismatch of the
transistors. Probably it would have been OK with a 20 ohm limiting resistor
and a 10 nF capacitor as a supply, or maybe by adding base resistance.

The LTSpice ASC for the simple driver follows:

Paul

==================================================================

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SYMATTR Value 3800p
TEXT -224 504 Left 0 !.tran 1m startup