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Formula for minimum drive current for mosfet

Discussion in 'Electronic Design' started by [email protected], Apr 10, 2008.

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  1. Guest

    Check out the data sheet. Figure 7 shows the typical gate charge
    required to get the gate voltage up to a level where the part is
    turned on - something like 10nC. The worst case total gate charge
    listed earlier in the data sheet is 24uC.

    20mA s going to take 1.2usec to deliver that 24uC of charge - this is
    slow switching by MOSFET standards, and you won't want to switch that
    slowly very often, because if you do there is a real risk that the
    switch will overheat.
  2. Why is slower going to going to cause it to heat up? Its less current so
    less heat (same amount of charge). In fact it probably would be better
    because its spread out over time. (like, say, charging a battery at 1A for 1
    year compared to 365A in one day. Same amount of charge but totally diffrent

    My switching is at most 100khz(its for motor control so anything about 20khz
    should be ok but I'm going for about 50khz). I figure I need about 5 to 10
    times this but really it shouldn't be that important(don't need it to be

    Really though, Can you explain to me why a slower switching speed will cause
    it to heat up more? It contradict's everything I know about transister
    switches and switching speed.
  3. The uC is not what will heat up, although at 100 kHz it could get a little
    warm. But the MOSFET will dissipate power during the time it is in its
    linear region during switching, and if you are controlling something like
    12V and 6A, you can have as much as 18 watts during this time. At 100 kHz,
    you could have 1 uSec of high power dissipation on each transition, every 5
    uSec, or 20% duty cycle, and about 3.6 watts of switching losses (as a
    rough estimate).

    I had problems driving an FQP24N08 at 100 kHz with the on-board 1 amp gate
    driver of a UC1843a, such that I was barely getting 75% efficiency with a
    12 V input at 40 watts output. It also has about 25 nC maximum gate charge.
    I was also losing about 1.2 watts in conduction losses with 0.05 ohms
    RdsOn. So I used a 6 amp gate driver UC3710, with an HUF75645 MOSFET, and I
    got close to 90% efficiency. This MOSFET has up to 238 uC gate charge, but
    its RdsOn is only 0.016 ohms, so I had less conduction loss. The driver
    gets a bit warm, too, so this is probably not an optimal combination. Just
    charging and discharging the 3800 pF gate capacitance takes a fair amount
    of power, probably about half a watt.

  4. Guest

    The maximum heat dissipation during switching occurs when the voltage
    across the switch is half way between the rails. The longer the time
    the drain takes to get from one rail to the other, the longer this
    dissipation keeps on happening.

    Spice can work it out for you if you model your load tolerably
    It ain't what you don't know that screws you up, but what you think
    you know that ain't so.

    You need to develop a better understanding of what is going on while
    the current through the switch moves from off to full on, and the
    voltage across the switch moves from the full rail voltage to
    practically nothing.

    In the middle of this process the instantaneous power dissipation in
    the swtich gets pretty high - you can work out exactly how high - and
    since the process takes a finite time - 10 to 20nsec if you know what
    you are doing, a microsecond or so if you cheapskate on the driver -
    each switching opertion dumps a predictable amount of energy into the
    switch junction.

    Work it out.
  5. Guest

    I believe what these posters are trying to say is that independent of
    the frequency of operation, you want to switch the fet quickly to stay
    out of the linear region. It is not the frequency, but rather the
    "squareness" of the driving voltage that is of concern. In addition,
    the posters were concerned with the "shoot through" or crowbar
    current, which can be avoided with a break before make circuit.

    The equation you were trying to think is the one for the average
    current used in driving a gate. You can probably derive it.
    I = dQ/dt , but in a "macro sense" we have a packet of charge Q
    transfered over a period T.
    Q=CV where C is the gate capacitance and V is the peak drive voltage
    1/dt is really the switching frequency F

    I = CVF.

  6. I think you need to work it out. You don't seem to have any clue what your
    talking about any just about any google search can prove you wrong.

    You might be right in that the maxmimum instantanous power dissipated in
    charging the capacitances is when V is half way min and max but what you
    fail to realize is that this is independent on frequency. (I might linger
    around Vpp/2 longer when switching slower but thats only if you take into
    account a single switch)

    I don't give a crap about what happens instantanous but average. Sure
    switching slower might mean that I'm at Vpp/2 longer but on average its the
    same if I switch as a frequency twice as fast. Why? Doubt you even read this
    but your at the Vpp/2 twice as many times... so it doesn't matter how fast
    you switch w.r.t to this power dissipation. Although you end up dissipating
    more power for other reasons when you switch faster.

    So, point being, If I switch at 2x the frequency I might only be at Vpp/2
    half as long but it occurs twice as often and hence cancels. THIS means that
    it doesn't matter which frequency I switch at and your logic of "Switching
    slower cause more power dissipation" is simply wrong.

    In fact almost every site I have seen gives a formula where the power
    dissipation is proportional to F and not inverse as you have said.
  7. gearhead

    gearhead Guest

    Jon, the problem is the amount of time it takes the mosfet(s) to
    transition from on to off and back from off to on again. During each
    switching action of a mosfet it acts like a resistor for the
    duration. Heat! So you want the duration of each switching event as
    short as possible, regardless of whether these events occur at 100Hz
    or 100kHz.
    But that's only part of the problem. Fred brings up a good point
    about cross-conduction.
    Now, when your drive has the gates pulled all the way to the rail
    (either one), that's no problem.
    But it IS a problem during the switching transition, because both
    mosfets are partly turned on providing a path -- not through the load,
    but directly across the power rails. You don't want slow switching
    So a weak drive is bad.
    For motor drive, a kilohertz is probably way plenty, and this lower
    frequency is better so that you don't put your mosfets in the hot seat
    so often.
  8. Ok guys, it seems we are talking about two different "Frequencies" here. One
    is the speed at which a transition occurs and the other is the number of
    times those transitions occur per second. The first really isn't a frequency
    since a frequency deals with something that is periodic(or at least that
    tends to be the way people think about frequencies).

    I do realize that the faster the transition the less power dissipation. That
    is pretty basic. And this is independent of frequency(up to a point).

    But even having this then the frequency, F, the # of transitions / second,
    will increase the power dissipation because we are simply transitioning more
    times per second.

    So what confused me was when you guys called the frequency of the transition
    and I thought it was the frequency of the # of transitions per second. (or
    maybe I added that to it or just confused the two).

    So we are both right ;) Its true that if you increase the transition speed
    that the power dissipation goes down, but if you increase the # of
    transitions/per second then the power dissipation goes up.

    Hopefully its obvious now...
  9. BTW, this should point to an optimal switching frequency for least power
    dissipation? Anyone know the formula?
  10. Its not so simple. I do see that now as I stated in the last post I made. I
    thought when they said frequency they meant something else and not the
    switchign time. (although you do make it much clearer than they did)

    But I cannot switch at any frequency and have as fast a transition as I
    want. I must drive the gates of the mosfet with BJT's and, of course, they
    have there own limits.

    Yes, I know.. its basically just like CMOS(I guess it is CMOS) and there is
    a short between tranistions.

    But there are a few solutions. One is to switch the mosfets on sequentially
    instead of at the same time. Al I loose is a bit of power to the motor
    momentarily but inertia should smooth it out. (basically delay the PWM a bit
    until the transition of the first fet is finished)

    But you do make a good point. The problem is, I do have limitations. I do
    see bill's point now about using a uC to drive the fets as its probably just
    way to low. Ultimately I'd like a formula for drive. (is it a simple RC
    circuit(Approximately) or more?)

    Well, I do understand that(and its more clear now that you said it). The
    thing about that slow of a frequency, from what I've read, is that its
    audiable(Which may or may not be an issue depending on how loud it is).

    Basically I need to maximize transition time and minimize frequency given
    all the contraints. (> 20khz(probably), surge current by drivers(bjt's),
    least power dissipation(Although I guess as long as its below max I'm ok)).

    Ok, I guess I see the confusion. The subject is minimum drive current for
    mosfets. I guess this is bad. I shouldn't require a minimum but a maxium
    within the mosfet drivers specs. (basically what I wanted was a formula to
    see the relationship)

    What I plan on doing is use bjt's to drive the gates in emitter follower...
    but I need to configure them for optimal conditions. (max drive current but
    within device specs)

    Anyways, thanks for the post. Its more clear now but I need to let it settle
    in. (I "knew" all the concepts before but there was just no glue tieing them
    together ;/)

    (Although I'd still like to drive them with the uC if possible because that
    is the simplest method... sure it might not be most efficient but if I'm
    still able to get reasonble power dissipation then its not *wrong* but just
    not optimal)

  11. Basically what I'm saying is, is that my drive can supply a surge current of
    X, I need to know how much power dissipation this gives. I know ultimately
    I'd want to supply as much as possible but, for example, I can't supply 15A
    because it has to go through the bjt and then I'll have to worry about power
    dissipation in that. (I also don't want to run the BJT's at max to get that

    I suppose I could use some other mosfets to drive the gates but seems like
    eventually I'll have diminishing returns?
  12. Guest

    The less frequently you switch your transistors, the less energy gets
    dumped into them, so you minimise switching losses by not switching.
    You don't need a formula to know that.

    There isn't much point in getting the power being lost in switching
    the transistors (dynamic losses) much below the power being dissipated
    in the transistors all the time there is current flowing through them
    (static losses).

    You've still got to heat sink the transistors well enough to get rid
    of the heat generated by the static losses, so you may well choose to
    have enough switching events per second so that your dynamic losses
    are about the same as your static losses. This makes for smaller and
    cheaper inductors and capacitors in your output filter than you'd need
    with fewer switching events. As you push the switching frequency
    higher you have to balance the need for bigger heat-sinks on your
    switches against further reductions in the size of the inductors and
    capacitors in the output filter.
  13. Guest

    There is a point where the transistor no longer sees average power but
    peak power. Never having designed in a power fet process, I don't know
    the design rule. In more general purpose semiconductor processes, the
    electromigration frequency limit is 1Khz. That is, a line that is
    being pulsed that you wish to consider receiving average current
    should be switching faster that 1KHz.

    Power MOSFETs do have SOA limits, but it is not as critical as with

    I like how you worry about everything. No, really. ;-) There is noting
    worse than getting product returned.

    If your intent is to drive directly from the uP, you may want to
    consider how the load switching will effect the uP. You will probably
    get ground bounce. In addition, as you increase VGS, there will be
    current flow from CDG. If the drain voltage is falling like a rock, it
    will generate current that opposes your gate drive. What I'm leading
    to here is you should probably buffer the uP from the power fet.
  14. I just finished looking into various MOSFET gate drivers for my design.
    They generally cost less than a dollar, and they really switch capacitive
    loads quickly, which cuts the switching losses quite a bit. Some good
    drivers from National, Maxim, TI, and Microchip are:


    I also played around with a homebrew MOSFET driver using an NPN and PNP
    transistor, and a few resistors and diodes, and it seemed to work pretty
    well in the simulator. I also set it up with a bootstrap to the MOSFET
    drain, with the idea that maybe a driver could be built into a MOSFET, but
    it's probably better to tie the voltage supply for the driver to a 5 volt
    or 12 volt supply. So you can omit some of this circuitry, but it is
    probably a good idea to have some sort of limiting resistor. I tried a
    simpler driver with an NPN and PNP with bases tied together as the input
    and emitters tied together as the output, with collectors across a 12 volt
    supply, and somehow there was simultaneous conduction and one of the
    transistors popped. Probably because they were not well matched. So here's
    a circuit you can try:



    Version 4
    SHEET 1 880 680
    WIRE 240 16 -384 16
    WIRE 32 64 -176 64
    WIRE 240 64 240 16
    WIRE 32 80 32 64
    WIRE 208 80 176 80
    WIRE 32 96 32 80
    WIRE -448 144 -512 144
    WIRE -176 144 -176 64
    WIRE -176 144 -448 144
    WIRE -32 144 -96 144
    WIRE 208 160 208 80
    WIRE 240 160 240 144
    WIRE 240 160 208 160
    WIRE -384 192 -384 16
    WIRE -272 240 -304 240
    WIRE -112 240 -128 240
    WIRE -96 240 -96 144
    WIRE -96 240 -112 240
    WIRE -16 240 -32 240
    WIRE 32 240 32 192
    WIRE 32 240 -16 240
    WIRE 64 240 32 240
    WIRE 192 240 64 240
    WIRE -512 256 -512 144
    WIRE -448 256 -448 144
    WIRE -304 272 -304 240
    WIRE -112 272 -112 240
    WIRE 64 272 64 240
    WIRE 240 272 240 256
    WIRE -16 288 -16 240
    WIRE -192 320 -192 240
    WIRE -176 320 -192 320
    WIRE -512 400 -512 320
    WIRE -448 400 -448 320
    WIRE -448 400 -512 400
    WIRE -384 400 -384 272
    WIRE -384 400 -448 400
    WIRE -304 400 -304 352
    WIRE -304 400 -384 400
    WIRE -192 400 -304 400
    WIRE -112 400 -112 368
    WIRE -112 400 -192 400
    WIRE -16 400 -16 352
    WIRE -16 400 -112 400
    WIRE 64 400 64 352
    WIRE 64 400 -16 400
    WIRE 240 400 240 352
    WIRE 240 400 64 400
    FLAG -304 240 Vin
    FLAG -16 240 Vgate
    FLAG -16 400 0
    SYMBOL voltage -304 256 R0
    WINDOW 3 -95 172 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    WINDOW 0 36 57 Left 0
    SYMATTR Value PULSE(0 5 50u 50n 10n 5u 10u 100)
    SYMATTR InstName V1
    SYMBOL res -176 224 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R1
    SYMATTR Value 200
    SYMBOL cap -32 288 R0
    SYMATTR InstName C1
    SYMATTR Value 3800p
    SYMBOL nmos 192 160 R0
    SYMATTR InstName M1
    SYMATTR Value SUM75N06-09L
    SYMBOL res 224 48 R0
    SYMATTR InstName R2
    SYMATTR Value 2
    SYMBOL voltage -384 176 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value 12
    SYMBOL res 224 256 R0
    SYMATTR InstName R3
    SYMATTR Value .05
    SYMBOL npn -32 96 R0
    SYMATTR InstName Q1
    SYMATTR Value 2N3904
    SYMBOL schottky -32 224 R90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName D1
    SYMATTR Value 1N5818
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 48 256 R0
    SYMATTR InstName R4
    SYMATTR Value 4.7k
    SYMBOL pnp -176 368 M180
    SYMATTR InstName Q2
    SYMATTR Value 2N3906
    SYMBOL res -80 128 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R5
    SYMATTR Value 5k
    SYMBOL res -176 416 R180
    WINDOW 0 36 76 Left 0
    WINDOW 3 36 40 Left 0
    SYMATTR InstName R6
    SYMATTR Value 5k
    SYMBOL schottky -192 224 M90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName D2
    SYMATTR Value 1N5818
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL cap -464 256 R0
    SYMATTR InstName C2
    SYMATTR Value 100n
    SYMATTR SpiceLine V=16 Irms=0 Rser=0.007 MTBF=0 Lser=0 ppPkg=1
    SYMBOL schottky 96 64 R90
    WINDOW 0 0 32 VBottom 0
    WINDOW 3 32 32 VTop 0
    SYMATTR InstName D3
    SYMATTR Value 1N5818
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL zener -496 320 R180
    WINDOW 0 24 72 Left 0
    WINDOW 3 24 0 Left 0
    SYMATTR InstName D4
    SYMATTR Value BZX84C12L
    SYMATTR Description Diode
    SYMATTR Type diode
    SYMBOL res 192 64 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R7
    SYMATTR Value 200
    TEXT -304 464 Left 0 !.tran 0 1m 0 startup
  15. gearhead

    gearhead Guest

    Did you use a resistors in each base, or just tie them together?
  16. Did you use a resistors in each base, or just tie them together?

    I just tied them together. It's basically two emitter followers. They
    should never be both on at the same time, but if one is slower than the
    other, I guess it can happen, and did. The simulation looked OK.

  17. gearhead

    gearhead Guest

    I haven't tried to use that totem pole myself, but I remember reading
    a comment somewhere by somebody that used two such totem poles in an H-
    bridge setup to drive a motor and said he had to use base resistors to
    avoid problems. The writer evinced some mystification as to why it
    should be so, but empirics rule!
    Fred is correct that in principle, you can't bias both transistors on
    simultaneously in that topology. Something else happened. Perhaps the
    transistors oscillated, and some parasitic effect may made it even
    worse. Base resistors would damp that.
    I think a little capacitance between base and collector will help tame
    high-strung behaviour as well.
  18. gearhead

    gearhead Guest

    As for the question of what frequency to use, you don't need a
    formula. You have set a minimum of 20 kHz because it would make noise
    below that. Going higher will just dissipate more power, so use

    If you find the uC is not enough and you have to use a driver chip,
    consider using a "high-low" or "half bridge" driver for two n-channel
    devices instead of the fairchild dual p and n. There are lots of such
    drivers available, and many incorporate deadtime to prevent cross-
    conduction. The only such chip I ever used was the IR2153, but you
    should look for the best one for your application.
    Besides avoiding the cross-conduction thing, you'll get more bang for
    the buck from n-channel mosfets.
    Here are a couple of links to those drivers.
  19. [snip LTspice]

    This developed from my problems with a fairly simple boost converter using
    a UC1843a driving a fairly large MOSFET. The FQP24N08 I originally used
    seemed to get too hot, and I thought it might be the 0.06 ohm RdsOn, so I
    used a beast MOSFET HUF75645 with 0.014 ohms. It drew more primary current
    and got hotter, so I assumed it was slow transition of drive voltage
    because of the 3800 pF gate capacitance, so I added a driver, and that
    seemed to fix it. Then I tried some ideas for a simple gate driver, and it
    became not so simple.

    But the LTspice simulations did not show that much higher dissipation with
    fairly slow transitions (up to about 1 uSec), which I was simulating with
    high values of series resistance and gate capacitance. I don't have exact
    models of the two transistors I used. I'm still a bit stumped as to why the
    UC1843a doesn't work well enough for the FQP24N08.

    I tried the simple NPN/PNP emitter follower gate driver because it seemed
    to work OK in LTspice, and it would be cheap and simple to add to the
    circuit. But the simulation was with 2N3904 and 2N3906, while I used an
    MPSA06 and an MJE170 (which I have lots of). The drive signal was directly
    from the gate driver of the UC1843a, which has a rise/fall time of 50 nSec
    into 1000 pF, and probably 10 nSec into just the bases, so it was probably
    fast enough to cause cross-conduction, especially with the mismatch of the
    transistors. Probably it would have been OK with a 20 ohm limiting resistor
    and a 10 nF capacitor as a supply, or maybe by adding base resistance.

    The LTSpice ASC for the simple driver follows:



    Version 4
    SHEET 1 1172 680
    WIRE -32 -144 -192 -144
    WIRE 384 -144 -32 -144
    WIRE 768 -144 384 -144
    WIRE 384 -48 384 -144
    WIRE -192 0 -192 -144
    WIRE 320 0 224 0
    WIRE 768 0 768 -64
    WIRE 832 0 768 0
    WIRE -32 16 -32 -144
    WIRE 384 80 384 48
    WIRE 480 80 384 80
    WIRE 512 80 480 80
    WIRE 640 80 640 -16
    WIRE 640 80 592 80
    WIRE 656 80 640 80
    WIRE 720 80 656 80
    WIRE 384 112 384 80
    WIRE -80 160 -112 160
    WIRE 0 160 -80 160
    WIRE 224 160 224 0
    WIRE 224 160 80 160
    WIRE 320 160 320 0
    WIRE 656 160 656 80
    WIRE -192 304 -192 80
    WIRE -112 304 -112 240
    WIRE -112 304 -192 304
    WIRE -32 304 -32 80
    WIRE -32 304 -112 304
    WIRE 224 304 -32 304
    WIRE 384 304 384 208
    WIRE 384 304 224 304
    WIRE 656 304 656 224
    WIRE 656 304 384 304
    WIRE 768 304 768 96
    WIRE 768 304 656 304
    WIRE 224 320 224 304
    FLAG 224 320 0
    FLAG 832 0 Vsw
    FLAG 640 -16 Vg
    FLAG -80 160 Vin
    FLAG 480 80 Vdrv
    SYMBOL voltage -112 144 R0
    WINDOW 0 37 59 Left 0
    WINDOW 3 -109 182 Left 0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V1
    SYMATTR Value PULSE(0 12 10u 10n 10n 5u 10u 1000)
    SYMBOL pnp 320 208 M180
    WINDOW 0 49 26 Left 0
    WINDOW 3 38 52 Left 0
    SYMATTR InstName Q2
    SYMATTR Value 2N4403
    SYMBOL res 96 144 R90
    WINDOW 0 0 56 VBottom 0
    WINDOW 3 32 56 VTop 0
    SYMATTR InstName R1
    SYMATTR Value 10
    SYMBOL res 496 96 R270
    WINDOW 0 32 56 VTop 0
    WINDOW 3 0 56 VBottom 0
    SYMATTR InstName R5
    SYMATTR Value 1
    SYMBOL voltage -192 -16 R0
    WINDOW 123 0 0 Left 0
    WINDOW 39 0 0 Left 0
    SYMATTR InstName V2
    SYMATTR Value 15
    SYMBOL nmos 720 0 R0
    SYMATTR InstName M1
    SYMATTR Value STB120NF10
    SYMBOL res 752 -160 R0
    SYMATTR InstName R6
    SYMATTR Value 2
    SYMBOL npn 320 -48 R0
    SYMATTR InstName Q3
    SYMATTR Value 2N3904
    SYMBOL cap -48 16 R0
    SYMATTR InstName C2
    SYMATTR Value 1µ
    SYMBOL cap 640 160 R0
    SYMATTR InstName C3
    SYMATTR Value 3800p
    TEXT -224 504 Left 0 !.tran 1m startup
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