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In FM mode, yes, IIRC. I'm using 3.5" HD disks which are usually recorded at
500k/sec in MFM mode with a spindle speed of (IIRC) 360rpm.
The problem is, without a data separator, the controller ICs are useless. FM
isn't too hard - I've got a schematic for that. MFM encoding, OTOH, is a
total PIB. I spent most of this morning searching through Google and the
EspaceNet patent information system. And what did I find? Nothing useful :-(
Thanks.
The MFM code is relatively painless to implement (more on that shortly). If
you're looking for patents, I have a proprietary paper from some years ago
that discusses myriad modulation codes, MFM among them, and points out that
until the mid-70's, MFM was used in all IBM disk and Ampex tape drives. The
origins of the code are disputed; the author provides three references:
1. W.H.P. Pouliart, J.P.H. Vandevenne, "Electrical Intelligent Storage
Arrangement," US Patent 2,807,004, issued Sept 17, 1957
2. Armin, Miller, "Recording and/or Reproducing System," US Patent
3,108,261, issued Oct 28, 1963 (Ampex).
3. G.V. Jacoby, "Magnetic Recording and Reproducing of Digital
Information," US Patent 3,414,894, issued Dec 3, 1968 (RCA).
Now, back to the code. The MFM encoding table is simply:
Data Code
0 B0
1 01
Since two code bits are written for each data bit, the code rate is twice
the data rate. The B in the B0 code means "the inverse of the previous code
bit." A moment's study will reveal that if the previous data bit was a 0,
the previous code bit was also 0, so the first code bit is 1. Similarly, if
the previous data bit was 1, the first code bit is 0.
Also, note that the encoded data consists of a meaningless bit followed by
the data bit. To decode MFM, simply save every other bit - but make sure
you get the right "other" bit.
The missing information is how to synchronize to the data pattern so you
get the right bit. At the start of each sector, there's a preamble, which
is a simple repeating pattern that the PLL uses to acquire timing. After
that, there's an address mark, which is a fixed pattern that's different
than the preamble. The preamble and address mark are the same for every
sector on the disk. Following the address mark is the data - a fixed number
of bytes. Following the data are one or two CRC bytes to check for data
corruption.
I'm not sure whether your floppy controller wants to see the encoded data
(as Jim's PLL data recovery circuit produces) or whether it wants to see
the recovered data. If it takes the encoded data, then you don't need any
of the information above. If it expects the data separator circuit to
decode the data before sending it to the controller, then you'll need to
add the address mark detector and a divide-by-2 for the clock going to the
data recovery flip-flop. The controller probably handled the error
correction testing, so you don't need to worry about that.
Last, it would be best to implement a clock-stopping scheme that prevents
glitches on the RCLK line. Controllers are often quite finicky about their
clocks, and are prone to making mistakes when they see glitches.
-- Mike --