# flip flop metastability

Discussion in 'Electronic Basics' started by Zerang Shah, May 25, 2006.

1. ### Zerang ShahGuest

Hello,

I've been doing some reading on metastability of flip flops when you
have inputs that are asynchronous or coming from a different clock
domain.

My question pertains to flip flops on the same clock domain. Suppose I
have a pair of rising edge D flip flops with the D line of one going
to the Q line of another. On the rising edge of the clock, the first
flip flop changes its state and output goes from low to high. At the
same rising edge, the second flip flop's input seems to violate the
hold time, right? We were low for nearly an entire cycle, then at right
after the rising edge the input changed.

Why do a pair of flip flops on the same clock domain not run into
metastability issues? Obviously I'm missing something here because
stuff like this is used all the time without problems.

Thanks for the help.

2. ### w2aewGuest

It's usually OK because the propagation delay of the first DFF will
cause the rising edge of the D input of the 2nd FF to be delayed far
enough behind the clock edge that it satisfies the hold-time on the 2nd
FF - i.e. the 2nd FF latches a zero during the first clock edge, then
latches a one for the next clock edge.

3. ### Zerang ShahGuest

I see, thanks for the help.

One more question about metastability. Suppose I have an asynchronous D
input to a DFF. Right at the rising edge my input goes from low to
high. This violates hold time and the DFF goes metastable. After the
metastable period ends (but before the next rising edge of the clock),
where does the DFF end up? Will the output be high, low or possibly
either?

4. ### Rich GriseGuest

If you are violating _both_ the setup and hold times, then you will
have a "race condition", and the output is not defined, i.e, it's
guaranteed to be either 1 or 0, but there's no way to predict which.

Hope This Helps!
Rich

5. ### Zerang ShahGuest

During setup, the async input changes from low to high. What will the
output settle as after metastable period?

During hold, the async input changes from low to high. What will the
output settle as after metastable period?

BTW can anyone recommend an "EE 101" type of book that covers issues
like this? I'm another "coder turned embedded guy".

6. ### w2aewGuest

There's no way to predict it. It could settle at either state. You
can't predict which state, or even how long it takes.
Same answer as above. If it was a predictable phenomenon, it wouldn't
be much of a problem.
There are techniques, but in the FF design, as well as implementation,
that can help to minimize the occurance of metastability in
asynchronous designs. However, being mainly an analog guy myself, I
can't give you a recommendation for a reference/text/etc. I'm sure
some of the digital experts here can recommend something for you.

7. ### Rich GriseGuest

I learned a lot from Don Lancaster's TTL Cookbook, but I don't remember
if he covered these types of cases. It might be worth looking at, if it's
still available anywhere.

Interestingly, just today, an ad for some website showed up on the NG,
which _might_ cover that - it seems fairly thorough, although I haven't
looked all that deeply into it:
http://www.interfacebus.com/Logic_Design_Descriptions.html

Good Luck!
Rich