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Final Report - Binary Sampler

Discussion in 'Electronic Design' started by Mike Monett, Nov 8, 2003.

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  1. Mike Monett

    Mike Monett Guest

  2. John Larkin

    John Larkin Guest

    Good grief, you again? How can you patent something that was in the GE
    transistor manual in 1964? And why don't you mention me in the
    credits, since I first told you about it here?

  3. Hello John,
    I am interested in a copy of that appnote? from the GE manual.
    Is there any link to it?

    Thanks in advance
  4. Mike

    Mike Guest

    Good luck.

    I notice that Souders' rates five references out of the fifteen [papers] in
    your report. I was under the impression you thought he didn't know what he
    was doing.

    -- Mike --
  5. John Larkin

    John Larkin Guest


    I'll (re)post the pics to a.b.s.e. I did a senior EE paper in 1969,
    "The Tunnel Diode Slideback Sampler", different circuits but similar
    idea - a threshold sampler with integrated bang-bang feedback - and
    won the student IEEE paper award, which meant I had to present the
    danged thing again at a regional competition. In my paper I made most
    of the same erroneous claims that MM is making now; I just never
    claimed to have invented it.

    The heterodyne sampler timebase idea is patented by LeCroy.

  6. Mike Monett

    Mike Monett Guest

    Thanks for your input.

    I don't claim to have invented the slideback sampler either, John.
    Nor do I claim having invented Delta Modulation, nor do I claim to
    have invented undersampling in conjunction with the Delta Modulator.
    The references I list show this clearly.

    If you look at the paper by T. M. Souders and P. S. Hetrick,
    "Accurate rf voltage measurements using a sampling voltage tracker,"
    IEEE Trans. Instrum. Meas., vol. IM-38, pp. 451-456, Apr. 1989, you
    will see he refers to S. P. McCabe's MS thesis, "A sampling voltage
    tracker for analyzing high speed waveforms", Univ. CA, Los Angeles,

    In the "History of the Idea", section 1.3 on page 2, McCabe credits
    Mr. Don Devendorf of the Hughes Aircraft Company for conceiving the
    basic idea in 1972. He continues

    "In 1974, when he presented the idea to me, it seemed that the
    circuit would be much more useful when coupled with a timing
    circuit which could generate a variety of strobe signals. Practice
    has borne this out, and the Sampling Voltage Tracker is now used
    in many applications where the use of an expensive oscilloscope is
    impractical or impossible."

    However, it appears that Devendorf, McCabe, Souders, and everyone
    else who worked on this concept failed to note the excellent noise
    rejection property obtained by undersampling the Delta Modulator or
    the Tracking ADC. I show a simulation of this effect and actual data
    taken from the demo circuit shown on my web site.

    Everyone also seems to have missed the periodic oscillation caused
    by low loop gain in the op amp, and the consequent loss of precision
    in sampler output. I show this on my web page at

    The switch to an undersampled Tracking ADC solves this problem. It
    is shown on the same page.

    If your IEEE paper covers these issues, I would certainly like to
    receive a copy. As I am moving, I will temporarily be without web
    access, but you could post it here so everyone else can see it also.

    The tunnel diode sampler is a different technology, and is not
    really well suited for precision waveform capture. There seems to be
    very few records of it being used other than in the GE manual. So
    unlike the quote above and the references I list, we really don't
    have proof that it functions well enough to be useful.

    It is prior art, but so are all the rest of the references I list.
    However, I tried to stay with references that other researchers
    could obtain fairly easily. For example, you can get the Souders
    paper in most good libraries, but they may not have a copy of the
    old GE transistor manual. You can also get the Souders paper online:

    As far as heterodyne sampling, there are probably several others
    besides the Lecroy patent. For exmple, see the Ainsworth patent
    5,260,670 (1993). These patents demonstrate prior art, but I believe
    the description shown on my web page is the first application of
    heterodyne sampling to a tracking ADC.

    Again, if your IEEE paper describes these issues, please post a copy
    so we can see it.

    Best Wishes,

    Mike Monett
  7. John Larkin

    John Larkin Guest

    I guess he never saw the GE manual either. Or maybe he did.
    No, they were smart enough to see how bad it really is.
    That's because most everybody (including me, in 1969) used a defined
    feedback step size per shot, not a simple lowpass filter, which is why
    yours can oscillate and the rest don't. Control theory is hardly new.
    It was the exact same concept, just different parts, and was as well
    suited to waveform capture as is a flip flop, namely mediocre compared
    to a real feedback sampler. Tek, HP, Philips, Anritsu, and LeCroy
    figured this out. There's a lot to be said for getting a, say, 10-bit
    linear error signal every shot instead of a 1-bit hint.

    To my knowledge, the 'binary sampler' was commercialized only once,
    and wasn't very successful. A diode half-bridge sampler performs
    vastly better at trivial incremental expense.

  8. Mike Monett

    Mike Monett Guest

    John Larkin wrote:

    I show why the current use of this technology can oscillate, such as the
    NIST sampling Tracker, and the McCabe thesis. The Tracking ADC solves it,
    as shown on my web site.

    An analog approach would be extremely difficult to keep balanced, and it
    would have the same problem with unequal up and down charge as a pure
    integrator. So I don't think your proposal would solve the problem.

    Then you pay the speed penalty when you have to average, as discussed on
    my web site. Pretty soon, the averaging time exceeds the time available
    for the measurement, or the system drifts. Then you cannot make the
    measurement with existing technology.
    You do not talk about the noise-rejection property of the Binary Sampler,
    and you do not include the poor noise figure of conventional samplers.

    Then, you have to include the time spent averaging in order to compare
    the results to the Binary Sampler. Also, the conventional diode sampler
    has a fairly drastic rolloff with frequency, as shown on my web site.

    Certainly, the diode sampler is faster and better suited for general
    purpose applications. But when you have an application where the Binary
    Sampler fits, it vastly outperforms the conventional diode technology.

    Best Wishes,

    Michael R. Monett
  9. John Larkin

    John Larkin Guest

    Down 3 dB at 70 GHz is 'fairly drastic'? That's what you can buy today
    from Tek, Agilent, LeCroy. PSPL has a 100 GHz sampler, but it's not a
    whole scope. On ebay, you can get a nice 7000-series rig, 5 GHz or so,
    for maybe $350.

    What's the measured (not simulated) bandwidth you are actually getting

  10. Mike Monett

    Mike Monett Guest

    I think the 7000 series goes up to 12 or 14GHz, depending on the sampling
    head. Yes, they are very cheap now, thanks to EBay.

    As shown on my web site, the 100EP52 will track a 200 ps risetime. The
    GigaComm part will probably do much better. As I mentioned on my web site,
    the Binary Sampler will never be as fast as conventional sampling scopes.

    But it really doesn't matter how cheap the current technology scopes are or
    how much bandwidth they have if they cannot make the required measurement.

    It would be difficult to package a HP or Textronix 70GHz scope in a small
    battery-powered instrument for remote applications, and the price would be
    prohibitive. If you used a homemade conventional diode sampler, you would
    end up with poorer performance than the Binary Sampler offers.

    You also keep forgetting the noise-rejection property of the Binary Sampler.
    In production applications, time is money. If you can make a measurement
    much faster, it generally pays for itself quickly. As shown on my web site,
    the difference can be quite dramatic.

    As I said before, none of these approaches will suit all applications. But
    where the Binary Sampler suits a need, it does so very well, and there
    happens to be a great deal of interest in it, primarily in Europe.

    Best Wishes,

    Michael R. Monett
  11. John Larkin

    John Larkin Guest

    All I saw on the web site seemed to be simulations. Was Fig 2 an
    actual measurement?
    Handheld battery-powered 150-200 ps TDRs use conventional diode
    samplers and are in everyday use; they look like calculators and are
    commodities these days. It takes very little power to run a diode
    sampler, even a fast one, certainly less than what a couple of EL
    chips burn up.

    The only time I tried making my own half-bridge sampler I got about 5
    GHz, 70 ps risetime, using a mediocre SOT-23 dual schottky and a
    flea-market SRD.
    You keep forgetting how bad it is. Median-seeking simulates well with
    perfectly symmetric noise, but sucks in real life. True averaging is
    correct. Besides, I'd rather have averaging be a option (as for eye
    diagrams or jitter measurements) than be mandatory.
    No human-readable waveform display needs more than 512 data points,
    1024 to ensure overkill. At 200 KSPS, like an older conventional
    sampler, that's 200 waveforms a second, more than anybody can use. 512
    points, 32x averaging still gives 12 waveforms per second. The reason
    sampling scopes don't sample faster is certainly not because they
    can't be made to do it, but rather because nobody cares.

    The heterodyne timebase *must* sample the entire period of the
    waveform, even if just one region is of interest, which is the common
    case. Zooming a region becomes a huge PITA. And 'sample' is a
    misnomer, since each 'point' must be, effectively, sampled thousands
    of times by the nature of the 1-bit information stream. And jitter is
    a real bear for a heterodyme timebase... your claim of 10 ps jitter
    between two plain vanilla crystal oscillators, over one second, is
    incredible: 1 ns would be pretty good.

    'Binary sampling' is a cute trick, is at least 40 years old, and isn't
    especially useful. I wish I'd never told you about it.

  12. Russell Shaw

    Russell Shaw Guest

    Anyone can make a high speed sampling gate. The real trick is
    to make the triggering circuit decent at 10GHz.
  13. Mike Monett

    Mike Monett Guest

    The Binary Sampler is now mirrored at

    Where I use simulated data in the description, I clearly mark the
    figure and show in the text it is simulated. In the "Binary Sampler
    vs Conventional Sampling" page at

    Figs. 1 and 2 are simulated noise with a conventional sampler. Figs.
    3 and 4 are actual data from the Binary Sampler.

    In the "Smoothing and Slew Rate Detect" page at

    Figs. 1 and 2 are actual data from the Binary Sampler.
    Yes, they are a marvel of low cost design. Any idea what the
    bandwidth is? I'd guess perhaps 1 GHz or so. Perfectly adequate for
    the application.

    For other applications, such as OTDR, averaging is needed to improve
    the SNR. I watched a line crew using a commercial unit, and it had
    to average 1,000 waveforms to get a result. This took a long time,
    and they had to repeat it each time they changed fibres.
    Interesting. Got the part numbers? Of course, you have the same
    problem with noise and low sample rate.
    The Binary Sampler does not respond to the amplitude of the error,
    so it cannot respond to the median. It only reponds to the direction
    of the error, which tends to zero in Gaussian noise.

    As Souders points out in "The effects of timing jitter in sampling
    systems," IEEE Trans. Instrum. Meas., vol. IM-39, Feb. 1991,
    averaging causes significant errors at slope changes.

    Since the Binary Sampler only responds to the direction of the
    error, and not the magnitude, it gives greater accuracy than
    conventional sampling under these conditions.

    Yes, you cannot measure noise with the Binary Sampler, as I mention
    on my web site. You need a conventional sampler or digitizer. But
    for many applications, the noise is well-defined and does not
    The required number of data points depends on what you need to
    measure. The 200KSPS is a real problem when you have to use
    averaging. Heterodyne sampling can be 1,000 times faster, so you get
    higher precision and faster throughput.
    You can use heterodyne sampling or a conventional delayed trigger,
    depending on the application. The conventional trigger will probably
    have more jitter and poor linearity.

    The point is you have a choice with the Binary Sampler. With a
    conventional sampler, you have no choice and are stuck with the low
    sample rate.
    The jitter spec is 25 picoseconds rms, and is pretty typical for
    these oscillators at 1MHz. I measured 24.7 ps with the HP5370A. I
    think the measurement interval was 10 seconds.

    I wrote the manufacturer and asked what the jitter spec was over a 1
    second interval. He did not have that information, but another
    similar vendor said the 1 second jitter was about 1/2.5 of the spec.

    I used a factor of 3.5 in the calculations to be conservative when
    comparing the Binary Sampler to the conventional sampler. This gave
    the conventional sampler a significant advantage, but the Binary
    Sampler still beat it.
    Sorry John, this is simply not true.

    You sent me the GE tunnel diode sampler gif via email after I had
    posted the description of the Binary Sampler to the web. You did not
    include a description of how the GE circuit worked, and you did not
    provide that information until much later.

    When you saw the information I had posted to the web, you claimed it
    would rail. Clearly, you did not understand it.

    Yes, as I show in the references, the basic idea has been around a
    long time. But nobody noticed the noise-rejection properties, or
    that the pure integrator would oscillate.
    Best Wishes,

  14. John Larkin

    John Larkin Guest

    We have, of late, done extensive testing on commercial crystal
    oscillators, with reference to jitter in the single-cycle range (which
    is what they spec, generally) out to seconds. A 3$ AT-in-a-can
    oscillator may well have ps sing;e-cycle jitter, but has a nasty
    corner in the millisecond range and increases to, typically, a
    nanosecond or three at one second delay. Thermally shielding it helps,
    a decent TCXO is better, ovenizing an SC-cut is better still, but
    picoseconds jitter per second of delay is *very* difficult.
    Is so. I told you about the d-flop feedback sampler in s.e.d. on Jan
    8, 2001, after which you decided you invented it, and announced you
    had "broken Shannon's Law" with it.

    Fortunately, Google archives all this stuff:


    That would be *very* interesting - do you have the time to explain

    How do you get a sampling bridge without taking a Tek or HP scope

    Best Regards,

    Michael R. Monett



    It's amazing how many people find a concept, obsess on it, and soon
    decide they invented it themselves.
    Again, after I told you about it. All archived.
    Why would a simple schematic need an explanation?
    As if!
    You assume that decades of engineers (including Shannon, and the
    staffs of HP and Tek, and of course your humble correspondent) are
    stupid, and you are smarter. Not likely.

  15. John Larkin

    John Larkin Guest

    That's not all that bad either. The HP 135 sampling scope did around
    20 ps jitter in 1960, with tubes.

  16. Mike Monett

    Mike Monett Guest

    John Larkin wrote:

    The spec is 25 ps. The HP5370 measures 24.7ps over an interval of 10
    seconds or greater. The Binary sampler would not display a 200ps risetime edge
    that had 1 ns of jitter. I have tried using an AD DDS with 330ps rms jitter,
    and can post the response of the Binary Sampler. The 200 ps risetime shows
    jagged edges. These disppear using the Hosonic 1 MHz crystals.

    Perhaps there is something wrong with your instrumentation. Please check using
    your HP5370.
    Yes, John. We were discussing using a binary search to locate the sample
    point. You showed a simple D flop. It had to work since a similar concept is
    used in flash converters.

    However, this was open loop. I closed the loop with an integrator. You said it
    would rail.
    Sorry John, I do not claim credit for Delta Modulation, the Tracking ADC, or
    the configuration shown in McCabe's thesis or the Souders NIST paper.
    Perhaps you are familiar with the circuit. To someone who has never used a
    tunnel diode, it is incomprehensible. However, it is irrelevant. The basic
    concept of the Binary Sampler was invented in 1972.
    Sure you did, John. Just look further in the same thread.
    John, conventional sampling techniques are interesting from a theoretical and
    practical point of view. The complexity attracts very intelligent people, and
    many spend their entire careers on it, such as Agoston.

    The thought of looking for a simpler approach is not part of their thinking. I
    was looking for a simpler approach, and was amazed to find the excellent
    noise-rejection properties of the Binary Sampler. To my knowledge, there are
    no other references to this phenomenon. If you can find one, please let me

    In the meantime, I am moving and have to shut down, so you get the last shot.
    I appreciate the excellent discussion and the time you have spent.

    Thanks John!

    Best Wishes,

    Michael R. Monett
  17. John Larkin

    John Larkin Guest

    This is complex. I guess what really matters is the phase noise during
    the real time interval that it takes the two oscillators to
    differentially traverse the risetime. For two 1 MHz oscillators 1 Hz
    apart, they sweep 1 microsecond per second, so they sweep across 200
    ps in 200 usec. Yeah, cheap oscillators are this good. The jitter
    *between* waveform features say 200 nsec apart (swept in 200
    milliseconds of real time) will be far worse. The math is a bitch
    The best a 5370 ever does is about 30 ps RMS, and it of course gets
    worse over long timebases due to oscillator phase noise. A 5370B also
    has an interesting jitter bump around 4 milliseconds, for reasons
    unknown. My Tek 11801A scope hits about 1.5 ps RMS, but only for
    short, sub-usec timebase delays.

    The only real way to measure the phase noise (or, time domain,
    jitter-versus-delay) over long timebases is to play two identical
    gadgets off against each other, carefully.

    Oh, a few more interesting points about the 1-bit sampler:

    PC Instruments did a commercial version for a while, and I'm fairly
    sure the Hypres 50 GHz superconductive sampling scope (it needed 120
    VAC plus a jug of liquid helium) was too. Both are out of production.

    An EP dflop does make a nice infinite-gain phase detector, capable of
    sub-ps locking in a PLL.

    Another - noisy - way to architect the sampler is to use a DAC for the
    feedback, but use a successive-approximation register rather than a
    counter. So for n-bit digitizing, you only need n samples.

    You heard it here first.

  18. Mike Monett

    Mike Monett Guest

    I'm not so sure I follow you here. The two positive transitions in the Binary
    Sampler data are 1uS apart, and the one on the right side of the graph is identical
    to the one on the left.

    We start recording data on the first phase match between the two oscillators. They
    are free-running, and show another phase match 1uS later. I guess the question is
    exactly how far apart are the two positive transitions. I can measure this to
    better than 1 ps in the graphics, so I will take a look after moving.
    The manuals are out of reach, but I believe a self-check for the HP5370 is to
    connect a coax between the rear panel 10MHz output and the input on the front
    panel. I measured 17ps rms, which I use in difference of squares to obtain the 25
    ps jitter of the crystal. I also have the high stability crystal option.
    Yes! Exactly. Wenzel has some great info and circuits on doing this, and I plan to
    get one set up as soon as possible.
    Probably would work very well. The EP52 jitter spec is 200fs, so all you need is a
    good reference and a low-noise vco. If the circuit is arranged the right way, it
    looks like the Binary Sampler, so you get the same noise-rejection.
    I think NIST uses a similar concept in their current version of the Sampling
    Voltage Tracker. See reference [13], O. B. Laug, T. M. Souders, and D. R. Flach, "A
    custom integrated circuit comparator for high-performance sampling applications,"
    IEEE Trans. Instrum. Meas., vol. 41, pp. 850-855, Dec. 1992.

    They use a SAR for the first few bits, then switch to a single bit increment to get
    the last bits. They pretty much have to do something like this, since you cannot do
    a binary search on noisy data.

    The problem with this approach is you lose the memory of the previous sample, so
    you lose the noise-rejection property of the Binary Sampler, and have to average to
    get rid of the noise. Then you run into system drift over long averaging times.
    Back in the same problem again:)
    Thanks, John. Very good discussion! I'm pulling the plug now - see you after I get
    to Midland.

    Best Wishes,

    Michael R. Monett
  19. Mike

    Mike Guest

    It's not as bad as you think, especially if you can neglect flicker noise.
    The flicker noise assumption is generally valid over short time intervals,
    but not over periods of one second. It should be noted that flicker noise
    makes the problems worse, not better, so neglecting it gives optimistic

    Assuming you can neglect flicker noise, the accumulated jitter of the
    oscillator is simply the period to period jitter multiplied by sqrt(N),
    where N is the number of cycles. This is the same as the standard deviation
    of a one-dimensional random walk after N steps. The math for this is easy -
    it's essentially one integral, and can be found in many statistics books. I
    can post a derivation on abse if you're interested.

    So, if you have a 1 MHz crystal oscillator with 25ps cycle-to-cycle jitter,
    the jitter over 1 second will be 25ns, relative to a perfect clock.
    Relative to another imperfect oscillator, it will be sqrt(2) times larger,
    since both oscillators are random-walking in different directions.

    I don't know what Mike's measuring - we'd need to see his test setup to be
    sure, but 24.7ps over 10 seconds or greater is hard to believe. The HP5370
    he's using claims an absolute accuracy of 65ps over a 10s interval, as long
    as the external timebase is that accurate, and a relative accuracy of 20ps.
    With an absolute accuracy of 65ps, any measurement of 24.7ps over the same
    interval would appear to be meaningless.

    -- Mike --
  20. John Larkin

    John Larkin Guest

    Hi, Mike,

    When I said the math is a bitch, I didn't mean it was hard to do,
    rather that the consequences are nasty for a heterodyne timebase.

    What MM's doing is using a 1 MHz oscillator to make a fast edge, and
    using a separate 1.000001 MHz oscillator as the timebase trigger for a
    sampler. So he's effectively sweeping 1 usec of equivalent time in 1
    second of real time, theoretically at 1 ps per sample. The question I
    had was the effect of oscillator phase noise in such a situation,
    especially using non-ovenized oscillators. A simple XO will typically
    accumulate about 1 ns error per second, often worse, so his timebase
    will jitter about like that. But a single 200 ps edge is swept in 200
    usec of real time, and the jitter *during* that single edge won't be
    bad. Of course, that edge will effectively wobble and wander around in
    time on successive sweeps.

    $3 Digikey-type crystal oscillators can, with luck, have maybe 10-30
    ps RMS jitter cycle-to-cycle, and accumulate jitter over longer
    intervals. There will typically be a jitter corner in the millisecond
    time frame, sloping up to, as I estimated, a ns or more at 1 second.
    Local transient temperature variations can make this much worse.

    When MM says "24.7ps over 10 seconds" I think he's actually measuring
    cycle-to-cycle jitter, but taking 10 seconds to make the ensemble
    measurement. That's a whale different from using the same oscillator
    to time a 10-second period, and measuring the jitter of *that*. No
    simple oscillator is going to be steady to a couple parts in 1e12 over
    10 seconds.

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