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fifo memory

Discussion in 'Electronic Basics' started by [email protected], Jun 4, 2005.

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  1. Guest

    I want to make some io interface which can read/write 64 bitpatterns
    from/to the LPT port. The FIFO must be synchronized
    on clock signals TXC and RXC.

    SENDING DATA TO LPT:
    minimum 64bit memory (to store x datapatterns) FIFO System
    *********************
    =TXC=======>* byte1-8 (1) *======>TX 8*8bytes LPT PC PORT
    * byte1-8 (2) *
    * byte1-8 (3) *
    DEVICE * byte1-8 (4) *
    * byte1-8 (5) *
    * byte1-8 (6) *
    =TX=64BITS=>* byte1-8 (7) *
    *********************

    RECEIVING DATA TO LPT:
    minimum 64bit memory (to store x datapatterns) FIFO System
    *********************
    <RXC========* byte1-8 (1) *<=====>RX 8*8bytes LPT PC PORT
    * byte1-8 (2) *
    * byte1-8 (3) *
    DEVICE * byte1-8 (4) *
    * byte1-8 (5) *
    * byte1-8 (6) *
    <RX=64BITS==* byte1-8 (7) *
    *********************

    The TXC and RXC is a 25kHz 10% duty cycle TTL block wave

    Please help me out with info and partnumbers...

    Kind regards, Geert De Coninck, Belgium
     
  2. Mark VB

    Mark VB Guest

    As I understand your question, you're not searching for a fifo, but a
    Serial/Parallel Shift register like the 74164 and a
    Parallel/Serial-Shift register like the 74165.


    HTH,
    Mark Van Borm
     
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