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field-programmable nanowire interconnect

Discussion in 'Electronic Design' started by Winfield Hill, Jan 17, 2007.

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  1. FPGA breakthrough paper in the January issue of Nanotechnology:
    "Nano/CMOS architectures using a field-programmable nanowire
    interconnect," by Gregory Snider and Stanley Williams of HP Labs.

    "Compilation of standard benchmark circuits onto FPNI chip models
    shows reduced area (8 × to 25 ×), reduced power, slightly lower
    clock speeds, and high defect tolerance..." 25 times, whew!

    The paper is available free for the next month or so on the IOP
    website, http://www.iop.org/EJ/abstract/0957-4484/18/3/035204
    Click on PDF.
     
  2. Robert

    Robert Guest

    Nano Crossbar switch interconnect on top of mostly standard CMOS.

    They mentioned the likelihood of high defect densities with the nano parts
    in the review I saw.

    Robert
     
  3. And discussed in the paper. Greatly reducing the transistor sizes
    leads to high defect rates, but the interconnects allow them to wire
    around the defects and use the chip at its full capability, even
    with up to 25% defect rate, IIRC. The full paper is worth reading.
     
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