FFT Address Generation Unit

[Deepthi]

Hi,
I am search of someone who can please help me with my project.
I have been working on a reconfigurable Address Generation Unit for FFT processors.
I need to Simulate it in MATLAB/SIMULINK and synthesise using FPGA ADVANTAGE in VHDL. Please let me know asap if you can do this for me. My mail ID is [email protected]

 

[NickS]

You need help or you want someone else to do it for you?

 

[Deepthi]

You need help or you want someone else to do it for you?

I need help. I want to learn what I am doing. Not just get it from someone else

 

[NickS]

Ok, I can tell you what works best. First you put forth a good amount of up front effort and then come back to us with the specific area that is giving you trouble. Give us background on how you arrived there and what is happening and someone with expertise in that area may be able to help.

If you don't have any idea how to start then you will probably need to start by finding a book or technical paper on the topic and do some reading. Perhaps Xilinx has an app note on that.

 

[Deepthi]

Thank You Nick for your support.

Well I am designing it using DIF Radix 2 FFT.
I have come up with a Structure for Datapath addressing which I should be implementing in MATLAB/Simulink & FPGA using VHDL.

How can I possible discuss about structure on tis forum I dunno...As am new to it !!!

 

[NickS]

So you are just using matlab to simulate your design before transferring it to the FPGA right? If so I would start by drawing a block diagram that shows the flow of your design. From there you can start coding with a meditated direction.

 

[Deepthi]

That would be very helpful.
Thank You very much.

The thing is that I need to do Matlab modelling & simulation and FPGA implementation of the same in FPGA Advantage environment and then compare the bit true results of the same.

If that is what you got then this is it !!!

 

[NickS]

Ok so lety me start by saying matlab is my friend. I am comfortable with it and I can be of assistance with the modeling. However I have a deep rooted disliking for FPGA design so you will need someone else to help you with that.

That said, what YOU need to do now is build your block diagram or flow chart(whatever you want to call it). Post a copy on this thread for us to see then If you need assistance implementing the matlab simulation that is where I can help you. But you need to show us your design flow next.

 

[Deepthi]

Hi Nick,
Well I have to design a base index generator. When I say base index it is nothing but indexing the output of a binary counter.

Well let me explain it clearly.

We have a 13-bit binary counter whose outputs are quoting to 4096 locations on a RAM and we have 13 such stages.
That is like the counter should count to 4K for 13 stages. Now we have to generate base index addresses for this 4K x 13 operations.
The idea I devised is to insert an extra bit '0' or '1' in the 13bit output of the counter.

Which wud be at the MSB position for the Stage 1 from count 0 to 4095 of that particular stage, then '0/1' at the MSB-1 position for Stage 2 from 0-4095, and MSB-3 for Stage 3 and so on till Stage 13(when we use the Big-Endian notation).

For doing this I have thought of using an Array of 13 MUXes to choose between the 1's and 0's and the position of insertion depending on the stage..

Can you please implement this for me in MATLAB or VHDL...if You have any further queries pls ask me..I will be very thankful to you pls

 

[(*steve*)]

Can you please implement this for me in MATLAB or VHDL.

How much are you paying to get this done?

Earlier you said you just wanted help. Now you want someone to do it for you.

 

[Deepthi]

You know what it is only a part of my design and I am giving you the idea...So I don't really think it is someone else doing it for me cause who ever helps me is gonna do what I want them to do for me following my sketch and not their own plot....alright...!!!

And if you are expecting some money for it how much do you want???

 

[NickS]

You know what it is only a part of my design and I am giving you the idea...So I don't really think it is someone else doing it for me cause who ever helps me is gonna do what I want them to do for me following my sketch and not their own plot....alright...!!!

And if you are expecting some money for it how much do you want???

Wow that post just buried you. I was going to throw together a block diagram for you but I think I am done here. What Steve was eluding to and what you clearly do not understand is that just because you have an idea doesn't mean you have contributed significantly to the design. I have lots of ideas too but I don't anticipate that anyone is going to take my ideas and go fully implement them for me. Bringing up money was a way of letting you know that people make a good living by taking ideas and implemented them( consultants are usually paid about $90/hour for that kind of work around here). That said I am not expecting any money. I am expecting you to do most of the leg work yourself.

I said I would help you with the matlab code, I never said I would do all the coding from scratch for you. By help I mean you code your design, then if/when it does not perform as you like I would look at it with a fresh pair of eyes and see if I can find what went wrong. Or if you lack understanding of some function I could explain what it is doing that is what help would be.

 

[Deepthi]

Apologies

I know I sounded weird on my post....sorry guys...sorry to Steve n Nick....take care