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FET capacitance lies?

Discussion in 'Electronic Design' started by Tim Williams, May 24, 2013.

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  1. Tim Williams

    Tim Williams Guest

    Does anyone have corroborating Coss vs. Vds data they're measured from
    various transistors?

    Case study: STP19NM50N. Datasheet shows a rather precipitous drop in Coss
    vs. Vds. I'm getting behavior in a circuit which is inconsistent with
    this. So I measured, using a pulsed method (apply CCS, measure dV/dt):
    Looks like a two exponent curve, probably consistent with Super Junction
    design or whatever.

    The datasheet has a rather awkward curve:
    I note that their graph appears to be drawn with a couple of bezier
    segments, which could simply be poorly adjusted. An engineer would hope
    for better, though.

    Here's an overlay comparison of the data:
    Surprisingly good agreement under 20V, then something goes wrong...

    Limitations: the method appears to have acceptable resolution at low
    voltages. I didn't crank it down to measure milivolts, so the lowest
    points (off scale, not shown) are buried in quantization noise. It
    doesn't measure very well under 100pF, since the CCS itself (a power PNP
    BJT) is somewhere around there (if I can trust the datasheet, it should be
    under 20pF at these voltages, though). Early effect shouldn't be a big
    deal, since it's a cascode CCS. Values at more than 100V or so aren't
    reliable because of Ccb rising as it begins to approach saturation (the
    CCS was suppled from 130V), and maybe gain reduction or Miller effect or
    something: this explains the rising tail in the data. Dynamic gain
    shouldn't be a terribly big problem, because the whole rising edge took
    70us; a measurement on an IGBT shows reasonable agreement with published
    data, and that produced a 30us edge.

    Surveying a number of similar products, ambiguous results are seen. ST
    and IR datasheets seem to show steps more often than others. IXYS almost
    never. Infineon sometimes shows one or the other, but sometimes also
    plots full range data on a linear axis, so all the interesting sub-50V
    behavior is squished away (perhaps they're trying to hide artifacts such
    as these?).

  2. Robert Baer

    Robert Baer Guest

    * So far so good; talking about FETs..
    * not a fet------------------------------------------------------------^
    * not a fet---------------------------------^
    * not a fet------------^
    * a 3rd beastie--------------^
    * Back to FETs..
  3. Robert Baer

    Robert Baer Guest

    I knew about the slope to the I/V curves in FETs, and knew that it
    was not due to "early Effect".
    Thanks for the enlightment.
  4. Tim Williams

    Tim Williams Guest

    I'm talking about FETs, do you have anything to say about them?
    Yes....and? It's called a test circuit, Bob.
    Still talking about the test circuit, Bob... it's called a "Limitations
    Section", a standard format, look it up.
    Back to.... nonsense?

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