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Ever unable to route PCB?

Discussion in 'Electronic Design' started by Mr.CRC, May 13, 2012.

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  1. Mr.CRC

    Mr.CRC Guest

    Hi:

    Picture this: 168-pin DIMM SDR-DRAM form factor 5.25in wide x 1.75in
    high, holding a 176-lead QFP (26mm sq., lead-to-lead), two of
    18.4x11.8mm 44-TSOPs, a 10x6.4mm 28-pin SOP, and a few other 3-5 pin
    little thingys.

    A whole crapload of bypass caps (about one per power pin of all ICs) and
    a few handfuls of pull resistors.

    All parts on topside, for this attempt, to avoid costs of assembling
    both sides.

    My first attempt has been to use 6 layers, with 2 dedicated to power,
    leaving 4 signal layers. Trace/space is 0.006in. Min drills are
    0.013in with 0.024in via diameters. These are a little large compared
    to similar boards, but to go to 0.012in and smaller drills invokes a
    modest cost knee which I am trying to avoid.

    Much of the difficult I'm currently facing is because the large via
    diameters are consuming a lot of space. So the first step I'll take if
    I can't route with these constraints is to allow 0.010in drill x 0.020in
    vias.

    A similar, though considerably higher pin count board is made by TI with
    10 layers. Another similar, but lower pin count board is made by TI
    with 6 layers. I'm making a variant of their (rare) 168-pin
    ControlCARD. Most of their ControlCARDs are 100-pin.


    I currently have all the power, bypass caps, power regulation, critical
    clock, reset, oddball, and analog traces routed and hopefully optimized
    to avoid cramping the style of the remaining digital tracks. I started
    with 499 connects, now down to 222.

    My next step is to see if the auto-router in Eagle 5.x can route the
    remaining traces. Then I will know it is theoretically possible.

    An initial attempt to run the autorouter Friday afternoon ended with the
    program stuck after just a few traces. Not encouraging, though I think
    there might be some parameters that I have to twiddle to get it to make
    more progress.

    What fun.
     
  2. Boris Mohar

    Boris Mohar Guest

    Try vias that have no annular ring on unused layers. 5/5 trace space is
    doable too.



    Regards,

    Boris Mohar

    Got Knock? - see:
    Viatrack Printed Circuit Designs (among other things) http://www.viatrack.ca

    void _-void-_ in the obvious place
     
  3. Mr.CRC

    Mr.CRC Guest


    That's an interesting idea. I doubt Eagle can handle this though. Ie,
    specifying an annular ring (restring) on specific layers, for specific vias.

    Also, the board houses I use would whine, but perhaps they could do it
    with their "custom" process.


    I seem to be having more success with my 2nd attempt, having put more
    thought into it this time before starting.
     
  4. Mr.CRC

    Mr.CRC Guest


    I've toned down some of the area taken by bypass caps and their vias.
    That seems to be helping.

    Most of my bus resistors are in little 8x0402 arrays.

    Once a lot of routing is done, it seems easy to find places to fit in
    pull resistors. So basically, they needn't be placed until near the end
    of the routing process.
     
  5. Uwe Hercksen

    Uwe Hercksen Guest

    Hello,

    some extra tolerance between the drill of the via and the adjacent
    traces is needed. Some misalignment between drills and trace layer may
    exist.

    Bye
     
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