Connect with us

Ethernet+FPGA

Discussion in 'Electronic Design' started by Mario Emmanuel, Aug 4, 2006.

Scroll to continue with content
  1. Hi all,

    I would like to connect directly an FPGA to a LAN Transformer.

    I have seen that usually this is done through an Ethernet ASIC controller (such as an
    LT97x).

    I wonder if it is possible to use differential I/O pins to directly drive Ethernet LAN
    transformer.

    Has anybody ever tried it?

    Thank you very much indeed for sharing your knowledge.
    Regards,
    Mario Emmanuel
     
  2. Marco T.

    Marco T. Guest


    Why don't use a Xilinx Virtex-4FX12?

    Marco
     
  3. Nico Coesel

    Nico Coesel Guest

    I've seen such a project somewhere. Try opencores.org first.
     
  4. Guest

    It should work in theory with 10Base-T, you might.. get away with 100Base-T.
    But I wouldn't be suprised by a "dead on arrival" ;)
     
  5. I would like to use another vendor for other reasons so I need to
    design custom VHDL Ethernet stuff.

    I am not worried about it, just wondering how to interface the LAN
    transformer from the FPGA I/Os.

    Thanks Marco,
     

  6. Thanks Nico,

    I already checked opencores before posting this. Despite there is an
    Ethernet MAC controller project I wasn't able to find the full
    schematic description on how to interface the FPGA I/Os to the LAN
    Transformer.
     
  7. Johnny

    Johnny Guest

    The OpenCores Ethernet MAC connects to a "PHY" through the MII port.
    The "PHY" (physical interface) is the one that connects to the magnetics
    ("LAN Transformer").

    So you'll need an FPGA+PHY+Magnetics.

    John.
     
  8. Thanks John,

    What about the posibility of desiging your own PHY using
    VHDL+differential I/Os or specific analogic drivers?

    It is not easy to find a distributor in Europe for small quantities
    (at least at a reasonable price).

    Regards,
    Mario
     
  9. John

    John Guest

    Hi Mario,

    I think several companies make PHYs now so that might help. PHYtec is
    one, SMSC might, have you checked around?

    It's possible to make the PHY using an FPGA+discrete logic but I think
    it will be very hard. The Ethernet signals are multi-level and the PHYs
    typically have some kind of DLL/PLL architecture to synchronize with the
    data stream. It's not trivial to implement that.

    I've thought about doing the same thing (more from an academic
    perspective) but that didn't really go anywhere.

    You might want to pose your questions on FPGA related Ethernet issues to
    this newsgroup:

    comp.arch.fpga

    FPGA related issues are discussed there.

    I check that group too :)

    Regards,
    John.
     
  10. Guest

    For the output just use two cmos outputs to drive the transformer, for
    the reciever
    LVDS would probably work

    -Lasse
     
  11. Mario,


    see fpga4fun.com, this guy beat you to it.

    You could probably do 10Base-T transmit maybe 10Base-T receive but not
    100Base-T and certainly not 1000Base-T. 10Base-T is manchester
    encoded. This is easy to generate and easy to decode. The device
    transmits only when a frame is being transmitted.

    Even if you did not hit the 802.3 IEEE spec of around 5V output,(see
    section 14 of 802.3 I forget the exact subclause) most 10Base-T
    receivers would receive it as a valid signal. On the receive side, I
    don't know FPGAs too well. You would want use something like a
    schmidtt trigger at the pad..

    100Base-T uses MLT-3 signaling, and transmits continuously on the TX
    pair since it recovers the clock from the waveform.

    1000Base-T uses MLT-3 and PAM-5 signaling on all 4 pairs in both
    directions and requires lots of DSP to cancel out cross talk from other
    pairs and a sophisticated analog front end to convert the PAM signal to
    digital. Not possible.

    regards.
    Kadir "Solid Gold" Suleyman
     
  12. joseph2k

    joseph2k Guest

    ISTR that 100basetx uses 25MSymbols/s at 4 levels AM for 100MBits/s
    signaling rate. AM direct from any logic levels seems alien somehow.
     
  13. Guest

    if it is just for a one-off for fun project, I guess it might be doable
    with two LVDS inputs
    biased at the midpoints of 0 to -1 and 0 to +1

    Tx could be done with some resistor and maybe two cmos outputs

    I'm tempted to try it out :)

    -Lasse
     
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day

-