Error in textbook?

[Paul Burridge]

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.

 

[John Larkin]

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.

Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John

 

[John Larkin]

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

p.

Note: for anyone using LTspice, the fet shown is not a working model;
I'm simply posting this as a diagram for illustration.

Oh, the skin depth equation on p 10 is apparently wrong, too.

John

 

[Paul Burridge]

Oh, the skin depth equation on p 10 is apparently wrong, too.

Excellent, John. Many thanks. It's reassuring you've seen the actual
book for yourself, but it would have been better if you'd have hung
fire until Active8 or someone else impulsive jumped in and accused me
of getting it all wrong. There are quite a few stoopid errors in this
otherwise excellent book. This one was just a bit more obvious than
the others.
Thanks again for the prompt response.

 

[Joerg]

Hi Paul,

Seems like it was meant for a MOSFET or someone typeset a wrong resistor
value and then all this got lost in the review process. Probably best to
let the author know so he can correct in the next ed.

I like this one! It reminds me of a mechanical engineering book I got from my late father in law, a book he received from someone even more senior. Under radio frequency waves it states that this is a wonderous and strange phenomenon that is yet to be explaineth. And here I am an RF guy...

Regards, Joerg

 

[fellow]

Hi all,

In his very skimpy explanation on basic DC biasing for FETs, Chris
Bowick (in RF Circuit Design) gives the suggested bias network that
I've posted to a.b.s.e under the same subject title as this message.
I don't see how this arrangement can possibly work for any N-Jfet
since for one thing at least, the gate is positive with respect to the
source. I've tried to scan the page in and post that, but the
scanner's messing about, so I've redrawn it as a spice schematic and
posted that instead. If it turns out the arrangement is incorrect, as
I suspect, I will endeavor to post his explanation for how he arrived
at these resistor values.
So: is he wrong or am I nuts?

Have a look on the inside flap to see if he's a reader in engineering at
some University. If so, then they probably are errors.

 

[Fred Bloggs]

Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards. The next
example on the same page illustrates that Vg must be near zero, not
+5. Really silly, putting these two circuits side-by-side.

John

Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

 

[John Larkin]

Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

Just shows you that an RF expert can't always handle DC.

John

 

[Active8]

Excellent, John. Many thanks. It's reassuring you've seen the actual
book for yourself, but it would have been better if you'd have hung
fire until Active8 or someone else impulsive jumped in and accused me
of getting it all wrong. There are quite a few stoopid errors in this
otherwise excellent book. This one was just a bit more obvious than
the others.
Thanks again for the prompt response.

Hey POS troll. How would you see it if I'm kill filed?

 

[Active8]

Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards.

Well, when you rearrange the Id eq to get Vgs, you get


[ ]
| |
| ( ) |
| | I | |
| | D | |
V = -Vp| sqrt| ------- | - 1 |
GS | | I | |
| | DSS | |
| ( ) |
| |
[ ]

You can swap the terms inside the brackets by moving the negative
sign of Vp inside, which gives you Bowick's version. Either way, you
get the wrong answer unless you recall that

sqrt(4) = +/- 2

So you have to apply some reasoning.

Thus (3 dots in a triangle) Burridge = idiot^100.

QED

 

[Active8]

LOL. That was an astute observation, not that I'm surprised. Either
I didn't read that part of the book ( I have a NOV '82 Siliconix
data book that sufficed) or I blew it off.

Good point. Bowick seems to be applying the jfet gate-voltage equation
backwards to enhance it! The other example on page 120 is even
sillier.

I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small
values of 2.48, yup. I better compare all his refs to my own
collection of app notes in der future and check the math.

Just shows you that an RF expert can't always handle DC.

It's his math, actually. See my other post and while you're at it,
reply to my reply to the idiot so he can see it. A blank post will
suffice >-)

 

[Active8]

Looks like the jfet will be saturated with the values shown, not good
for RF work. Looks like he got the sign of Vgs backwards.

Well, when you rearrange the Id eq to get Vgs, you get

[ ]
| |
| ( ) |
| | I | |
| | D | |
V = -Vp| sqrt| ------- | - 1 |
GS | | I | |
| | DSS | |
| ( ) |
| |
[ ]

You can swap the terms inside the brackets by moving the negative
sign of Vp inside, which gives you Bowick's version. Either way, you
get the wrong answer unless you recall that

sqrt(4) = +/- 2

So you have to apply some reasoning.

Strike that. I'd didn't work. Gots me wondering WTF now.

 

[Active8]

On Thu, 12 Aug 2004 19:12:04 -0400, Active8 wrote:

Strike that. I'd didn't work. Gots me wondering WTF now.

.
. . Burridge = idiot^100.
^^^^^^^^^^^^^^^^^^^^
That still works for all values of idiot > 1.

Otay. You write the node eq for Vgs, expand Shockley's eq., equate
the two, rearrange, solve the quadratic and pick the correct root.

Sorry I thrashed around on that.

 

[John Larkin]

I *do* remember reading *that*. 0 + 2.48 = 0 for sufficiently small
values of 2.48, yup.

Now *that's* funny!

Too bad Paul won't see it!

John

 

[Active8]

Now *that's* funny!

Too bad Paul won't see it!

John

Based on some recent posts, I suspect that duplicitous white trash
POS is reading my posts despite his blasting JT for "not sticking to
his [ctrl-k] guns" just to see what I'm saying behind his back. It's
not really backstabbing since it's out in the open and I'd say it to
his face before I rearrange it like so much algebra.

I think he needs a good old fashioned hillbilly ass-whoopin' what
with the way he's flaming a few of us and making hillbilly slurs.

Apologies again for the multiple replies to self while working this
out. That Siliconix book used design curves and iterative stuff.

I'd be impressed if SFB Burridge (rhymes with porridge - like the
space between his audio sensors) could solve the bias net (or any
net) on his own.

 

[Ken Smith]

Shhhh...don't tell the resident idiot, but it's going to be damn tough
biasing that IDSS=5mA JFET to a quiescent ID=10ma....

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.

 

[Paul Burridge]

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.

How many mS did the Fet last? I suppose you could always stand there
with a can of arctic spray directed on it, but I doubt the customer
would be impressed. ;-)

 

[Fred Bloggs]

How many mS did the Fet last? I suppose you could always stand there
with a can of arctic spray directed on it, but I doubt the customer
would be impressed. ;-)

Actually there have been systems produced that did run quite hot and
were arranged with a liquid nitrogen drip onto the electronics to keep
things cool.

 

[Mike Andrews]

Actually there have been systems produced that did run quite hot and
were arranged with a liquid nitrogen drip onto the electronics to keep
things cool.

One model of Seymour Cray's computers ran with the logic immersed in
a bath of chilled Fluorinert or some such, with a fairly hefty pump
to keep the coolant recirculating through the chiller.

--
Paul Raj Khangure mumbled:

Every time someone calls Java a programming language a fairy dies?

From frustration, if nothing else.
DaZZa, in a.t-s.r

 

[John Larkin]

Theres no problem getting 10mA to flow in a FET with Idss of 5mA. Just
apply a positive bias to the gate. I've had as much as 2 or 3 A flow
through a JFET this way.

Jfets make pretty good pA-leakage diodes, although the series
resistance tends to be higher than for a "real" diode. Never tried one
as a power rectifier.

Jfets don't enhance much, but gaasfets - especially phemts - enhance a
lot, typically 1.6 * Idss just before the gate begins conducting in
earnest. That can be useful.

John