EMC advice - MSP430 design - 4 layer Vs 2 layer

[Pooh Bear]

I'm working on a new "light industrial" product based around an MSP430F436.
The product is a battery / external powered data logger which sleeps waking
every 1/2ms or so to check some sensors. It is used for data logging only -
ie non-critical applications.

Has anyone had any experience EMC testing similar MSP430 based designs?

I haven't. I've done loads of other stuff though.Why do you think it's processor
specific ?

Other facets of the design include:

*LCD - non muxed updating around 32Hz, always on.
*Serial interface accessed intermittently
*Micro clock xtal = 32768 Hz
*Linear regulator power supply.
*The enclosure is a mix of metal/plastic and is unlikely to be grounded.
*Very little else in the way of clocked logic, no oscillators or high
current switching etc.
Irrelevant.

My thoughts are that a 2 layer board with plenty of ground plane either side
etc should be sufficient.

You're ( barely ) scratching the surface frankly.


Graham

 

[Frithiof Andreas Jensen]

My thoughts are that a 2 layer board with plenty of ground plane either side
etc should be sufficient.

probably - avoid cutting slots in it and there might be sense in locating
some app-notes on how to make an "island" for the CPU and laying out,
filtering & shileding for industrial equipment; motor drives and arch
welders are not good neighbours!

Any comments advice welcome!

The lower the clock frequency, the lower the current consumption and the
more embedded (i.e. the smaller the size), the more quiet your circuit will
be.

This does not mean that it cannot be disturbed by external EMI. Just that it
does not emit much.

 

[John Woodgate]

I read in sci.electronics.design that Frithiof Andreas Jensen

This does not mean that it cannot be disturbed by external EMI. Just
that it does not emit much.

Reciprocity! If it's a smaller sending antenna, it's a smaller receiving
antenna.

 

[Stephen]

You might want to take a look at "Printed Circuit Board Design
Techniques for EMC Compliance" by Mark Montrose. I found it pretty
helpful.

4 layers is good. Keep all loops as small as possible. Don't make
slots in the ground and power planes. Not having a switching dc-dc
converter makes things easy.

Stephen

 

[Rob Gaddi]

I'm working on a new "light industrial" product based around an MSP430F436.
The product is a battery / external powered data logger which sleeps waking
every 1/2ms or so to check some sensors. It is used for data logging only -
ie non-critical applications.

Has anyone had any experience EMC testing similar MSP430 based designs?


Other facets of the design include:

*LCD - non muxed updating around 32Hz, always on.
*Serial interface accessed intermittently
*Micro clock xtal = 32768 Hz
*Linear regulator power supply.
*The enclosure is a mix of metal/plastic and is unlikely to be grounded.
*Very little else in the way of clocked logic, no oscillators or high
current switching etc.

My thoughts are that a 2 layer board with plenty of ground plane either side
etc should be sufficient.

Any comments advice welcome!

thanks
rob

I've got a proto that I did using a 430 on a 2 layer board. It was
designed to be compliant, but never got as far as testing so who knows.
The fact that the current consumption on the processor is so absurdly
low should do you some favors on the emissions front, again just make
sure that you know where the return current for every signal will be
flowing and try to keep the plane on the non-component side as
continuous as possible, even if it costs you some extra vias (make sure
there are decoupling caps by the vias). Also, the usual advice about
putting your decoupling caps near the ICs, between the vias and the
package pins goes double, triple, n-ple.

 

[Paul Burke]

Reciprocity! If it's a smaller sending antenna, it's a smaller receiving
antenna.

What FAJ was saying is that a slow clock speed (and though he didn't say
it slow edges) means that there's less energy at higher frequencies to
transmit in the first place. It's still susceptible to those higher
frequencies though.

Paul Burke

 

[Paul Burke]

My thoughts are that a 2 layer board with plenty of ground plane either side
etc should be sufficient.

Lay the power circuits out on the oldfashioned grid plan. Don't pack it
too tight, then flood both sides with grounded copper. Plenty of extra
vias to stitch the copper areas together as much as possible- what you
are trying to do is get an approximation to a continuous ground plane,
with every signal track having a parallel ground track all along, or at
least to ensure that loops are as small as possible. I've had a good
deal of success with this approach, but you have to put in a lot more
work than for 4 layer, and it's slow and tedious.

Paul Burke

 

[John Woodgate]

What FAJ was saying is that a slow clock speed (and though he didn't
say it slow edges) means that there's less energy at higher frequencies
to transmit in the first place. It's still susceptible to those higher
frequencies though.

I was referring to:

" ...and the more embedded (i.e. the smaller the size),..."

 

[Martin Riddle]

Unless you want to futz with getting a 2 layer board to work, go for the 4 layer board.
The real problem in the slew on the clock edges, not the clock speed.
If your carefull you can get a 2 layer board to be compliant, but its work. Cost factor analysis time.

Cheers

 

[Rob]

I'm working on a new "light industrial" product based around an MSP430F436.
The product is a battery / external powered data logger which sleeps waking
every 1/2ms or so to check some sensors. It is used for data logging only -
ie non-critical applications.

Has anyone had any experience EMC testing similar MSP430 based designs?


Other facets of the design include:

*LCD - non muxed updating around 32Hz, always on.
*Serial interface accessed intermittently
*Micro clock xtal = 32768 Hz
*Linear regulator power supply.
*The enclosure is a mix of metal/plastic and is unlikely to be grounded.
*Very little else in the way of clocked logic, no oscillators or high
current switching etc.

My thoughts are that a 2 layer board with plenty of ground plane either side
etc should be sufficient.

Any comments advice welcome!

thanks
rob

 

[Keith Williams]

I haven't. I've done loads of other stuff though.Why do you think it's processor
specific ?

It can be. I did some pre-compliance testing in a previous job. I
found that a package (same processor) that a customer was about to use
would have caused them much EMI grief. I found the problem in time to
swap the package, though it was a little tougher to meet their specs in
the lesser performing package.

Irrelevant.

What's irrelevant? Plastic in the package is certainly important, as
is current switching. Saying all of the above is irrelevant is, well,
nuts.

You're ( barely ) scratching the surface frankly.

Come on...

 

[Rob]

I haven't. I've done loads of other stuff though.Why do you think it's processor
specific ?



You're ( barely ) scratching the surface frankly.


Graham

Graham - I mentioned the processor as all higher speed short switching time
signals on the data/address buses etc are internal to the package - this
must surely be an advantage as far as emissions are concerned.


While I may only be scratching the surface, many of us work at different
levels using different approaches. I've been through the EMC testing loop
with around 10 different products over a 6 year period and managed to kludge
my way though successfully with all of them. I've tried reading through
books on the subject most of which barely mention practicalities - at the
end of the day the local test lab owner with his 25+ years of experience is
a great source of practical methods. Members of this NG also share their
knowledge.

You intimate that you have a in-depth knowledge of this field, do you have
any practical advice to offer? Thanks for the reply.

Rob

 

[Robert Lacoste]

My thoughts are that a 2 layer board with plenty of ground plane either
side
etc should be sufficient.

My guess is that a 2-layer board, I mean a properly designed two-layer board
will very probably be enough on the emission side. HOWEVER the situation
could be very different on the immunity side : You are reading captors, are
they analog ones ? What is the resolution & precision you are targeting ?
Bandwidth ? What is the level of noise that your application can tolerate ?
This could change the recommandation to 4-layers quickly depending on your
actual requirements...

Friendly yours,

 

[Pooh Bear]

Graham - I mentioned the processor as all higher speed short switching time
signals on the data/address buses etc are internal to the package - this
must surely be an advantage as far as emissions are concerned.

It is indeed. I prefer this route too when possible.

While I may only be scratching the surface, many of us work at different
levels using different approaches. I've been through the EMC testing loop
with around 10 different products over a 6 year period and managed to kludge
my way though successfully with all of them. I've tried reading through
books on the subject most of which barely mention practicalities - at the
end of the day the local test lab owner with his 25+ years of experience is
a great source of practical methods. Members of this NG also share their
knowledge.

Having a good source of practical knowledge is a great help.

I was lucky enough to find a tame consultant back in 1987 when I first got
involved ( in this case with submitting products for testing to the American FCC
part 15 subpart J - computing devices rule ).

You intimate that you have a in-depth knowledge of this field, do you have
any practical advice to offer? Thanks for the reply.

It's reasonable. A few thoughts at random Keep any fast signal traces short *and
minimum LOOP AREA*. Use RCs if the signal edges aren't needed to be ultra fast.
Some recent microcontrollers now have 'controlled slew rate' I/O pins - use
them. Watch for noise emanating from the power leads ! One could write a sermon
? on *proper* grounding and enclosure design.

Have you considered immunity too ?

I doubt you're likely to have too much trouble with emissions from the sound of
it though.

The fun'll start with any interface cables no doubt.

The reason I mentioned that 2 layer boards is only scratching the surface is
that it's perfectly possible to make a 2 layer board that performs badly and a
single sided one that performs well ! Philips have written some decent
Application notes about doing single sided well for comsumer apps.


Graham

 

[Pooh Bear]

What FAJ was saying is that a slow clock speed (and though he didn't say
it slow edges) means that there's less energy at higher frequencies to
transmit in the first place. It's still susceptible to those higher
frequencies though.

Indeed - therefore keep those loops small ! It even works improving the
performance of audio products ( in the audio band ).

Graham

 

[Nico Coesel]

Unless you want to futz with getting a 2 layer board to work, go for the 4 layer board.
The real problem in the slew on the clock edges, not the clock speed.
If your carefull you can get a 2 layer board to be compliant, but its work. Cost factor analysis time.

I doubt clock edges are a problem in MSP430 designs. The outputs have
a very low output current. Perhaps TI has an application note on this
topic.

 

[Dieter Brozio]

Lay the power circuits out on the oldfashioned grid plan. Don't pack it
too tight, then flood both sides with grounded copper. Plenty of extra
vias to stitch the copper areas together as much as possible- what you

In my opinion as much as possible, but not so much that it looks like
the result of a fired shotgun, because even the smalest via is a hole
in the ground plane.

are trying to do is get an approximation to a continuous ground plane,
with every signal track having a parallel ground track all along, or at

ACK. With this method I got the best EMI and immunity results in a former
project.

least to ensure that loops are as small as possible. I've had a good
deal of success with this approach, but you have to put in a lot more
work than for 4 layer, and it's slow and tedious.

Sure, it depends on the saled units. If you sell 10 mill/year, what are
further three weeks of development time accumulated to the more profit
with a 2 layer PCB? (But of course I agree that a 4 layer is the better
technical solution.)

Dieter

 

[rob]

Thanks for all the feedback guys. You have given me some good material. I
think for the sake of simplicity we might go 4 layer on this one.
regards
rob