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electrical level conversion

K

Kurt Kaiser

Jan 1, 1970
0
Hi there,

I'm currently having a serious problem: I got an LVPECL clock synthesizer
and I want to connect it to several clock inputs on my FPGA. The FPGA
features 2 LVDS interfaces, whereas each LVDS pair is located at opposite
sides of the device, meaning there will be some extensive routing to do. I
designed a resistor network for the level conversion from LVPECL to LVDS.
What I'd like to know now is
a) Can I route the 2x2 lines (two times differential to the two opposite
sides of the FPGA) one-to-one out of my clock device to the inputs or should
I use a dedicated buffer / repeater IC for clock distribution?
b) If clock buffer are needed, should I use LVPECL buffers and do the
conversion to LVDS level afterwards or should I perfom the conversion before
the buffer and then use an LVDS IC?
c) Where should I place the level conversion network? Is is better to place
it right at the LVPECL output or is it more advisable to do it right before
the FPGA inputs after a transmission line length of about 7 cm?
Any help, comments, advice is highly appreciated!

Thank you all very much.
Kurt
 
J

John Larkin

Jan 1, 1970
0
Hi there,

I'm currently having a serious problem: I got an LVPECL clock synthesizer
and I want to connect it to several clock inputs on my FPGA. The FPGA
features 2 LVDS interfaces, whereas each LVDS pair is located at opposite
sides of the device, meaning there will be some extensive routing to do. I
designed a resistor network for the level conversion from LVPECL to LVDS.
What I'd like to know now is
a) Can I route the 2x2 lines (two times differential to the two opposite
sides of the FPGA) one-to-one out of my clock device to the inputs or should
I use a dedicated buffer / repeater IC for clock distribution?
b) If clock buffer are needed, should I use LVPECL buffers and do the
conversion to LVDS level afterwards or should I perfom the conversion before
the buffer and then use an LVDS IC?
c) Where should I place the level conversion network? Is is better to place
it right at the LVPECL output or is it more advisable to do it right before
the FPGA inputs after a transmission line length of about 7 cm?
Any help, comments, advice is highly appreciated!

Thank you all very much.
Kurt

Do you need level conversion at all? Some FPGA lvds inputs will work
fine with lvpecl drive.

But why does the fpga need two identical clocks? What kind of fpga are
you using? I sure hope you're not doing a single synchronous logic
system driven by two clock inputs!

John
 
K

Kurt Kaiser

Jan 1, 1970
0
John Larkin said:
But why does the fpga need two identical clocks? What kind of fpga are
you using? I sure hope you're not doing a single synchronous logic
system driven by two clock inputs!

I'm using Virtex-4 FX60. Depending on the implemented designs I will use
either the clock input on one side or the other, not both the at the same
time of course. So I'm hoping for more flexibility and freedom of clock
routing if I have two clocks available and stick to the one that fits better
from design to design. The FPGA's input is LVDS.

Bye

Kurt
 
J

John Larkin

Jan 1, 1970
0
I'm using Virtex-4 FX60. Depending on the implemented designs I will use
either the clock input on one side or the other, not both the at the same
time of course. So I'm hoping for more flexibility and freedom of clock
routing if I have two clocks available and stick to the one that fits better
from design to design. The FPGA's input is LVDS.

Bye

Kurt

OK,


<-----fpga----->

pecl+ ----r1-------------------0----------------0----+---r3------ gnd
|
r2
|
pecl- ----r1-------------------0----------------0----+---r3------ gnd


something like that maybe. The r1's are very close to the pecl source,
and the terminators are fairly close to the fpga's second clock pair.
The differential impedance of the traces should slam into a matching
termination, r2 || 2*r3.

Check the common-mode range of the fpga lvds receivers. It shouldn't
take much voltage shifting to get the lvpecl into the legal lvds
range. On a Spartan3, I don't think it would take any at all.

What sort of Vccio range do these V4's use? They keep going down.

One of my guys spent a lot of time - too much time - trying to reduce
jitter on a signal that passes through a S3 chip a few times. He did
all sorts of exotic stuff to the off-chip circuits, oscillators
comparators and such. I finally took a look at it yesterday. Turns out
there's an ldo furnishing the 1.2 volt core voltage, and it had a 22
uF ceramic cap across its output, and it was oscillating, a nice 100
mV sawtooth at 24 KHz. That was of course modulating the prop delay of
the fpga!

Looks like I'm going to break one of my rules and replace the 1206
ceramic cap with a tantalum.

John
 
P

PeteS

Jan 1, 1970
0
John said:
OK,


<-----fpga----->

pecl+ ----r1-------------------0----------------0----+---r3------ gnd
|
r2
|
pecl- ----r1-------------------0----------------0----+---r3------ gnd
Ok if there is no stub to clock destination 1, otherwise I would split:

pecl+ ------r1----------------------------------------0---r3-------- gnd
| CK1 r2
pecl- ------r1---------|------------------------------0---r3--------gnd
| |------------------------------0---r3--------gnd
| CK2 r2
|----------------------------------0--r3--------gnd

for a fully terminated solution. Depends on layout, clock speed,
allowable mismatch, over/undershoot etc. John's would probably work; I'd
only use this where really really necessary.
something like that maybe. The r1's are very close to the pecl source,
and the terminators are fairly close to the fpga's second clock pair.
The differential impedance of the traces should slam into a matching
termination, r2 || 2*r3.

Check the common-mode range of the fpga lvds receivers. It shouldn't
take much voltage shifting to get the lvpecl into the legal lvds
range. On a Spartan3, I don't think it would take any at all.

For LVDS on Spartan (and V4 I believe), the user provides Vref, so it's
just a matter of providing the appropriate Vref, AFAICT.
What sort of Vccio range do these V4's use? They keep going down.

One of my guys spent a lot of time - too much time - trying to reduce
jitter on a signal that passes through a S3 chip a few times. He did
all sorts of exotic stuff to the off-chip circuits, oscillators
comparators and such. I finally took a look at it yesterday. Turns out
there's an ldo furnishing the 1.2 volt core voltage, and it had a 22
uF ceramic cap across its output, and it was oscillating, a nice 100
mV sawtooth at 24 KHz. That was of course modulating the prop delay of
the fpga!


Looks like I'm going to break one of my rules and replace the 1206
ceramic cap with a tantalum.

John

I have an LDO that requires an output resistance of no less than 0.5
ohm, (0.5 - 5 ohm is stated, IIRC), so rather than use a tant, I use a
ceramic with a 0.5 ohm in series with it - that way at least I don't
have to deal with the issues of tants, and the effective ESR maintains
over temp a whole lot better than a tant.

Cheers

PeteS
 
J

John Larkin

Jan 1, 1970
0
Ok if there is no stub to clock destination 1, otherwise I would split:

pecl+ ------r1----------------------------------------0---r3-------- gnd
| CK1 r2
pecl- ------r1---------|------------------------------0---r3--------gnd
| |------------------------------0---r3--------gnd
| CK2 r2
|----------------------------------0--r3--------gnd

for a fully terminated solution. Depends on layout, clock speed,
allowable mismatch, over/undershoot etc. John's would probably work; I'd
only use this where really really necessary.

It *will* work!
For LVDS on Spartan (and V4 I believe), the user provides Vref, so it's
just a matter of providing the appropriate Vref, AFAICT.


On S3, the lvds inputs don't need a vref; they're basically diff-input
comparators. It's just a matter of whether they can handle the
common-mode voltage of the pecl's. Don't know about V4's.
I have an LDO that requires an output resistance of no less than 0.5
ohm, (0.5 - 5 ohm is stated, IIRC), so rather than use a tant, I use a
ceramic with a 0.5 ohm in series with it - that way at least I don't
have to deal with the issues of tants, and the effective ESR maintains
over temp a whole lot better than a tant.

Too late for me! I could build a teepee on the 1206 pads, but
production hates teepees. "Look, engineering did another teepee!"

What we should have done is use a cheap LM1117 and a 22 uF aluminum
cap. 1.25 volts is close enough.

John
 
P

PeteS

Jan 1, 1970
0
John said:
It *will* work!



On S3, the lvds inputs don't need a vref; they're basically diff-input
comparators. It's just a matter of whether they can handle the
common-mode voltage of the pecl's. Don't know about V4's.


Too late for me! I could build a teepee on the 1206 pads, but
production hates teepees. "Look, engineering did another teepee!"

What we should have done is use a cheap LM1117 and a 22 uF aluminum
cap. 1.25 volts is close enough.

John

I have in front of me the latest and greatest from Xilinx on S3A and it
states (in IO standards) that it directly supports LVPECL.

Cheers

PeteS
 
J

John Larkin

Jan 1, 1970
0
I have in front of me the latest and greatest from Xilinx on S3A and it
states (in IO standards) that it directly supports LVPECL.

Cheers

PeteS


Should work, as long as Vccio is the same as the lvpecl supply. So
eliminate the r1's.

John
 
K

Kurt Kaiser

Jan 1, 1970
0
Thanks for your answers so far. I cannot use the flexibility with Vccio
(which is a wonderful feature for the normal I/Os) since I'm referring to
the MGTCLK_IN inputs for the RocketIOs. They only support LVDS input
signals.

Maybe I'm totally wrong but wouldn't it be even better to design the clock
distribution as a chain rather than a "branch connection"? What I mean is:

LPECL Clock Output ---> Resistor Network ---> MGTCLK_IN_1 ---> MGTCLK_IN_2
 
J

John Larkin

Jan 1, 1970
0
Thanks for your answers so far. I cannot use the flexibility with Vccio
(which is a wonderful feature for the normal I/Os) since I'm referring to
the MGTCLK_IN inputs for the RocketIOs. They only support LVDS input
signals.

Maybe I'm totally wrong but wouldn't it be even better to design the clock
distribution as a chain rather than a "branch connection"? What I mean is:

LPECL Clock Output ---> Resistor Network ---> MGTCLK_IN_1 ---> MGTCLK_IN_2

That might work OK if the distances are all short and the resistor
values are low; "short" is relative to the lvpecl risetime. The
situation is complex here, but the bottom line is that either the
MGTCLK_IN_1 or the MGTCLK_IN_2 inputs will see non-ideal waveforms.
How non-ideal depends on the resistive network, the distances, and the
trace impedances.

Your circuit could work if the Vertex can be programmed to terminate
the #2 clock pair and not terminate #1, and the differential trace
impedance matches this value. I don't know if they can do this. As I
recall, the terminations can be programmed in some of the Spartan LVDS
diff pairs.

The circuit that I drew can deliver ideal (ie, square) waveforms at
both loads, if the differential impedance of the traces matches the
termination impedance, as I noted.

Since you can hardly believe a stranger in a newsgroup, you should
really get direct advice from someone who really understands
transmission-line effects. There are lots of ways to get this wrong.

John
 
P

PeteS

Jan 1, 1970
0
John said:
That might work OK if the distances are all short and the resistor
values are low; "short" is relative to the lvpecl risetime. The
situation is complex here, but the bottom line is that either the
MGTCLK_IN_1 or the MGTCLK_IN_2 inputs will see non-ideal waveforms.
How non-ideal depends on the resistive network, the distances, and the
trace impedances.

Your circuit could work if the Vertex can be programmed to terminate
the #2 clock pair and not terminate #1, and the differential trace
impedance matches this value. I don't know if they can do this. As I
recall, the terminations can be programmed in some of the Spartan LVDS
diff pairs.

The circuit that I drew can deliver ideal (ie, square) waveforms at
both loads, if the differential impedance of the traces matches the
termination impedance, as I noted.

Since you can hardly believe a stranger in a newsgroup, you should
really get direct advice from someone who really understands
transmission-line effects. There are lots of ways to get this wrong.

John

As John notes, it's not a simple problem [if it was, you could get the
answer at WalMart ;) ]

I've done what you want, but every board is different, as are the jitter
and non-ideal behaviour that can be tolerated (PCBs induce jitter, as do
discontinuities of any description on a transmission line).

I fully agree with John; get direct advice from someone versed in
transmission line effects. For the LVDS inputs from PECL drive, I am
surprised no-one from Xilinx has chipped in, but because I am
interested, I'll pull the datasheet for V4 later on and see what it says
about input range etc.

Cheers

PeteS
 
H

Hal Murray

Jan 1, 1970
0
I fully agree with John; get direct advice from someone versed in
transmission line effects. For the LVDS inputs from PECL drive, I am
surprised no-one from Xilinx has chipped in, but because I am
interested, I'll pull the datasheet for V4 later on and see what it says
about input range etc.

The Xilinx people are probably on comp.arch.fpga
 
P

PeteS

Jan 1, 1970
0
PeteS said:
John said:
That might work OK if the distances are all short and the resistor
values are low; "short" is relative to the lvpecl risetime. The
situation is complex here, but the bottom line is that either the
MGTCLK_IN_1 or the MGTCLK_IN_2 inputs will see non-ideal waveforms.
How non-ideal depends on the resistive network, the distances, and the
trace impedances.

Your circuit could work if the Vertex can be programmed to terminate
the #2 clock pair and not terminate #1, and the differential trace
impedance matches this value. I don't know if they can do this. As I
recall, the terminations can be programmed in some of the Spartan LVDS
diff pairs.
The circuit that I drew can deliver ideal (ie, square) waveforms at
both loads, if the differential impedance of the traces matches the
termination impedance, as I noted.

Since you can hardly believe a stranger in a newsgroup, you should
really get direct advice from someone who really understands
transmission-line effects. There are lots of ways to get this wrong.

John

As John notes, it's not a simple problem [if it was, you could get the
answer at WalMart ;) ]

I've done what you want, but every board is different, as are the jitter
and non-ideal behaviour that can be tolerated (PCBs induce jitter, as do
discontinuities of any description on a transmission line).

I fully agree with John; get direct advice from someone versed in
transmission line effects. For the LVDS inputs from PECL drive, I am
surprised no-one from Xilinx has chipped in, but because I am
interested, I'll pull the datasheet for V4 later on and see what it says
about input range etc.

Cheers

PeteS

The common mode range for LVDS inputs on V4 is stated to be:

Min: 0.3V
Typ: 1.2V
Max: 2.2V

The typical PECL output common mode voltage is 1.775 to 1.975V (properly
terminated, of course), so I see no problem directly driving the device.

As the differential input can provide 100 ohm diff across the pair, if
you drive with 100 diff lines (and make sure it's a proper diff pair)
you can probably drive the inputs directly [one caveat, below] (although
I'd hedge my bets and leave pads for external terminations.

So the short answer is:

according to the data sheet, you should be able to drive the LVDS inputs
with a PECL signal and be within the common mode range, _but_ the PECL
signal may be too large (differentially). The V4 datasheet shows a
maximum input diff voltage for these inputs at 600mV, but PECL (any ECL)
can drive at higher levels than this, so a signal attenuator may be
required. If you aren't happy with the common mode, the attenuator could
be used to translate the DC level ;)


Cheers

PeteS
 
J

John Larkin

Jan 1, 1970
0
PeteS said:
John said:
On Thu, 14 Dec 2006 08:35:43 +0100, "Kurt Kaiser"

Thanks for your answers so far. I cannot use the flexibility with
Vccio (which is a wonderful feature for the normal I/Os) since I'm
referring to the MGTCLK_IN inputs for the RocketIOs. They only
support LVDS input signals.

Maybe I'm totally wrong but wouldn't it be even better to design the
clock distribution as a chain rather than a "branch connection"? What
I mean is:

LPECL Clock Output ---> Resistor Network ---> MGTCLK_IN_1 --->
MGTCLK_IN_2



That might work OK if the distances are all short and the resistor
values are low; "short" is relative to the lvpecl risetime. The
situation is complex here, but the bottom line is that either the
MGTCLK_IN_1 or the MGTCLK_IN_2 inputs will see non-ideal waveforms.
How non-ideal depends on the resistive network, the distances, and the
trace impedances.

Your circuit could work if the Vertex can be programmed to terminate
the #2 clock pair and not terminate #1, and the differential trace
impedance matches this value. I don't know if they can do this. As I
recall, the terminations can be programmed in some of the Spartan LVDS
diff pairs.
The circuit that I drew can deliver ideal (ie, square) waveforms at
both loads, if the differential impedance of the traces matches the
termination impedance, as I noted.

Since you can hardly believe a stranger in a newsgroup, you should
really get direct advice from someone who really understands
transmission-line effects. There are lots of ways to get this wrong.

John

As John notes, it's not a simple problem [if it was, you could get the
answer at WalMart ;) ]

I've done what you want, but every board is different, as are the jitter
and non-ideal behaviour that can be tolerated (PCBs induce jitter, as do
discontinuities of any description on a transmission line).

I fully agree with John; get direct advice from someone versed in
transmission line effects. For the LVDS inputs from PECL drive, I am
surprised no-one from Xilinx has chipped in, but because I am
interested, I'll pull the datasheet for V4 later on and see what it says
about input range etc.

Cheers

PeteS

The common mode range for LVDS inputs on V4 is stated to be:

Min: 0.3V
Typ: 1.2V
Max: 2.2V

The typical PECL output common mode voltage is 1.775 to 1.975V (properly
terminated, of course), so I see no problem directly driving the device.

As the differential input can provide 100 ohm diff across the pair, if
you drive with 100 diff lines (and make sure it's a proper diff pair)
you can probably drive the inputs directly [one caveat, below] (although
I'd hedge my bets and leave pads for external terminations.

So the short answer is:

according to the data sheet, you should be able to drive the LVDS inputs
with a PECL signal and be within the common mode range, _but_ the PECL
signal may be too large (differentially). The V4 datasheet shows a
maximum input diff voltage for these inputs at 600mV, but PECL (any ECL)
can drive at higher levels than this, so a signal attenuator may be
required. If you aren't happy with the common mode, the attenuator could
be used to translate the DC level ;)


Cheers

PeteS

I might modestly suggest that my little circuit shifts the DC level
down, reduces the AC swing, terminates the differential trace
impedance, furnishes the pecl pulldown current, and presents the same
clean square wave to both fpga clocks, all independent of trace
lengths.

John
 
J

Jim Thompson

Jan 1, 1970
0
[snip]
according to the data sheet, you should be able to drive the LVDS inputs
with a PECL signal and be within the common mode range, _but_ the PECL
signal may be too large (differentially). The V4 datasheet shows a
maximum input diff voltage for these inputs at 600mV, but PECL (any ECL)
can drive at higher levels than this, so a signal attenuator may be
required. If you aren't happy with the common mode, the attenuator could
be used to translate the DC level ;)


Cheers

PeteS

I might modestly suggest that my little circuit shifts the DC level
down, reduces the AC swing, terminates the differential trace
impedance, furnishes the pecl pulldown current, and presents the same
clean square wave to both fpga clocks, all independent of trace
lengths.

John

Careful there, John. "Modestly suggest"(ing) is looked upon around
here as a sign of weakness... no matter that you are perfectly correct
;-)

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
[snip]
according to the data sheet, you should be able to drive the LVDS inputs
with a PECL signal and be within the common mode range, _but_ the PECL
signal may be too large (differentially). The V4 datasheet shows a
maximum input diff voltage for these inputs at 600mV, but PECL (any ECL)
can drive at higher levels than this, so a signal attenuator may be
required. If you aren't happy with the common mode, the attenuator could
be used to translate the DC level ;)


Cheers

PeteS

I might modestly suggest that my little circuit shifts the DC level
down, reduces the AC swing, terminates the differential trace
impedance, furnishes the pecl pulldown current, and presents the same
clean square wave to both fpga clocks, all independent of trace
lengths.

John

Careful there, John. "Modestly suggest"(ing) is looked upon around
here as a sign of weakness... no matter that you are perfectly correct
;-)

...Jim Thompson


But I don't care a f***** f*** whether anybody here thinks I'm weak or
strong or weird or anything else. Why should I care what other people
think?

Oh, just found a cool bug in our gated-oscillator DPLL. When we start
the 50 MHz oscillator, the offset voltage of a nearby LM7301 opamp
(the one that drives the varicap) jumps about 25 mV, and the control
loop _does_ give a f***** f*** about that! So I need a fairly fast (4+
MHz) opamp in sot-23, LM7301 pinout, +9 supply, that's fairly
insensitive to front-end rf rectification. There aren't many jfet amps
in that package! Maybe one of the new ADI "industrial cmos" things
would work.

Dang, I was going to watch a Lord Peter episode tonight. I guess I'll
be prowling opamp datasheets instead.

John
 
R

Rich Grise

Jan 1, 1970
0
But I don't care a f***** f*** whether anybody here thinks I'm weak or
strong or weird or anything else. Why should I care what other people
think?

Yeah, but you can afford that attitude because you're already Kewl! ;-)

Cheers!
Rich
 
K

Kurt Kaiser

Jan 1, 1970
0
John Larkin said:
Your circuit could work if the Vertex can be programmed to terminate
the #2 clock pair and not terminate #1, and the differential trace
impedance matches this value. I don't know if they can do this. As I
recall, the terminations can be programmed in some of the Spartan LVDS
diff pairs.

Unfortunately the MGTCLK_IN inputs have a built-in termination, so I see a
problem in terminating #2 clock pair and not terminating clock #1 !? Has
anyone made experiences with the RocketIO clock inputs, yet?
 
J

Jim Thompson

Jan 1, 1970
0
On Thu, 14 Dec 2006 16:42:57 -0700, Jim Thompson
[snip]
Careful there, John. "Modestly suggest"(ing) is looked upon around
here as a sign of weakness... no matter that you are perfectly correct
;-)

...Jim Thompson


But I don't care a f***** f*** whether anybody here thinks I'm weak or
strong or weird or anything else. Why should I care what other people
think?

Oh, just found a cool bug in our gated-oscillator DPLL. When we start
the 50 MHz oscillator, the offset voltage of a nearby LM7301 opamp
(the one that drives the varicap) jumps about 25 mV, and the control
loop _does_ give a f***** f*** about that! So I need a fairly fast (4+
MHz) opamp in sot-23, LM7301 pinout, +9 supply, that's fairly
insensitive to front-end rf rectification. There aren't many jfet amps
in that package! Maybe one of the new ADI "industrial cmos" things
would work.

Dang, I was going to watch a Lord Peter episode tonight. I guess I'll
be prowling opamp datasheets instead.

John

Is Lord Peter Wimsey playing on TV, or do you have it on DVD?

I've recently been watching some "Monk" re-runs.

...Jim Thompson
 
J

John Larkin

Jan 1, 1970
0
On Thu, 14 Dec 2006 16:42:57 -0700, Jim Thompson
[snip]
Careful there, John. "Modestly suggest"(ing) is looked upon around
here as a sign of weakness... no matter that you are perfectly correct
;-)

...Jim Thompson


But I don't care a f***** f*** whether anybody here thinks I'm weak or
strong or weird or anything else. Why should I care what other people
think?

Oh, just found a cool bug in our gated-oscillator DPLL. When we start
the 50 MHz oscillator, the offset voltage of a nearby LM7301 opamp
(the one that drives the varicap) jumps about 25 mV, and the control
loop _does_ give a f***** f*** about that! So I need a fairly fast (4+
MHz) opamp in sot-23, LM7301 pinout, +9 supply, that's fairly
insensitive to front-end rf rectification. There aren't many jfet amps
in that package! Maybe one of the new ADI "industrial cmos" things
would work.

Dang, I was going to watch a Lord Peter episode tonight. I guess I'll
be prowling opamp datasheets instead.

John

Is Lord Peter Wimsey playing on TV, or do you have it on DVD?


Netflix. There's one series done in the early 90's that's superb; they
do the stuff with Harriet, Strong Poison and Gaudy Night. Now we're
into the older ones, early 70's, with a much different Lord Peter -
much more piffle - and no romance, just Bunter and murders.

Good stuff. And we're on the waiting list for the next season of
Deadwood.

Oh, AD8065 looks good.

http://www.analog.com/en/prod/0,,759_786_AD8065,00.html

John
 
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