# electret microphones & connecting.

Discussion in 'Electronic Design' started by Adam. Seychell, Dec 25, 2004.

I recently bought some Panasonic WM-61A electret microphones and found
lots of discussion on the web about people modifying them to increasing
dynamic range. The internal FET is normally connected as common source.
The normal connection diagram of the microphone is;

,-----.
| |
2.2k |
| |
o-------- output
| |
|| electret|| D |
||diaphragm||--- G (FET) o +
|| || S 2.0V
| | o -
| | |
`--------------------o-----'--- GND (case)

The modifications talked about suggest inserting a 10k resistor between
source and GND and omitting the drain resistor by supplying 9V directly.
This configuration would make the FET a voltage follower, and I would
like to know exactly how this can achieve greater SPL from the device as
claimed by others. I'm skeptical because there is no explanation.

To my own thinking the electret diaphragm can be modeled as a AC voltage
source coupled to the gate via a small capacitance (around 10pF).
Here the link to the Panasonic datasheet and a typical microphone FET
from Sanyo.

http://service.semic.sanyo.co.jp/semi/ds_pdf_e/TF202.pdf
http://www.panasonic.com/industrial/components/pdf/em06_wm61_a_b_dne.pdf

According to the Panasonic WM-61A specs of typical 0.018 V/pascal
sensitivity with a 2.2k drain resistor then at an extreme sound of say
140dB SPL (or 20 pascals) this calculates to a AC drain current of
20*0.018/2200 = +-160uA.

In the conventional common source configuration, the FET is operated in
saturated mode with Id = Idss. Looking at the Id vs Vgs graph of the
above FET , it shows that a change in Id of about +-160uA. The curve in
this range still remains relatively linear with respect to Vgs (the
electret voltage). Miller capacitance cannot play a roll since the
frequency response of the microphone remains flat in most of the audio
spectrum. The typical forward transmittance of the FET is 1.2mS so a
delta Id +-160uA corresponds to Vgs of +-130mV, which is also the
electret driving voltage at 140dB SPL.

Now for the (modified) common drain configuration the FET operates as a
voltage follower. At 140dB SPL the AC output voltage will be +-130mV and
have a DC bias of 10kOhm*Idss or somewhere between 2 and 5. Anyone care
to tell me if my calculation are wrong because I cannot see the
advantage of the modified common drain FET configuration.

2. ### Rich GriseGuest

As long as you're doing all that arithmetic, do it at a few data points
_less than_ 140 dB SPL for both configurations, and see what the graph
looks like.

Good Luck!
Rich

more mods on