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Edge-Triggered S-R Flip-Flop

J

Jim Thompson

Jan 1, 1970
0
ISTR that there was recently a discussion of how to make an
Edge-Triggered S-R Flip-Flop... a rising edge on one input sets the
flop, a rising edge on the other input resets.

I should keep notes... I can't remember how it was done.

Anyone still have a copy?

Thanks!

...Jim Thompson
 
J

James Meyer

Jan 1, 1970
0
ISTR that there was recently a discussion of how to make an
Edge-Triggered S-R Flip-Flop... a rising edge on one input sets the
flop, a rising edge on the other input resets.

I should keep notes... I can't remember how it was done.

Anyone still have a copy?

Thanks!

...Jim Thompson

I thought they all worked like that.

Unless you mean that the DC level on either input is arbitrary. In that
case maybe you can program a PIC to do the job. :cool:

Jim "the other one"
 
J

Jim Thompson

Jan 1, 1970
0
I thought they all worked like that.

Unless you mean that the DC level on either input is arbitrary. In that
case maybe you can program a PIC to do the job. :cool:

Jim "the other one"

What's a PIC? Ah, yes, what Picadores use ;-)

...Jim Thompson
 
M

mike

Jan 1, 1970
0
Jim said:
ISTR that there was recently a discussion of how to make an
Edge-Triggered S-R Flip-Flop... a rising edge on one input sets the
flop, a rising edge on the other input resets.

I should keep notes... I can't remember how it was done.

Anyone still have a copy?

Thanks!

...Jim Thompson

I'd use a gate-delay "differientiator" on each input of an S-R flop.
You can also do some interesting things with a two-bit Johnson Counter
with separate edge clocked inputs for S and R. Decode the output
states with an xor gate.
mike

--
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J

Jim Thompson

Jan 1, 1970
0
I'd use a gate-delay "differientiator" on each input of an S-R flop.
You can also do some interesting things with a two-bit Johnson Counter
with separate edge clocked inputs for S and R. Decode the output
states with an xor gate.
mike

I just invented a method that avoids the "delay-game"... I'll post it
tomorrow... it's time now for Cab/Merlot blend and a filet ;-)

...Jim Thompson
 
K

Keith R. Williams

Jan 1, 1970
0
Jim- said:
I just invented a method that avoids the "delay-game"... I'll post it
tomorrow... it's time now for Cab/Merlot blend and a filet ;-)

Does it get rid of metastability too? ;-)
 
T

Tom Del Rosso

Jan 1, 1970
0
Jim said:
ISTR that there was recently a discussion of how to make an
Edge-Triggered S-R Flip-Flop... a rising edge on one input sets the
flop, a rising edge on the other input resets.

I should keep notes... I can't remember how it was done.

Anyone still have a copy?

Thanks!

With 2 flip flops, or with 8 NAND gates. Replace them with NORs and
swap the outputs for negative edge trigger.

OUT
|
|
+-------|--------------------------+
| | |
| | +-------------+ |
| | | | |
^ | | | ^ | |
| *********** | | | *********** |
| * R * | | | * R * |
+---*D Q*--+ | +---*D Q*--+
* * | * *
* _* | * _*
+---*CLK Q*O------+ +---*CLK Q*O
| * * | * *
| *********** | ***********
| |
| |
| |
SET RESET


I traced the circuit below with 4 possible initial states.

below: Q(initially) = 0 RESET = 0


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \6 +--| | /7x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| /5 | |
|NAND>-----+ |
\4 +-------| +--| Q
| |NAND>--+------- /3
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- \4
/3 +-------| +--|
|NAND>--+ \4x |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 0 RESET = 1


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \6 +--| | /7x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| /5 | |
|NAND>-----+ |
\4 +-------| +--| Q
| |NAND>--+------- /3
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- \4
/3 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 0


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \2 +--| | /3x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =0 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 1


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \2 +--| | /3x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|
 
J

Jim Thompson

Jan 1, 1970
0
With 2 flip flops, or with 8 NAND gates. Replace them with NORs and
swap the outputs for negative edge trigger.

OUT
|
|
+-------|--------------------------+
| | |
| | +-------------+ |
| | | | |
^ | | | ^ | |
| *********** | | | *********** |
| * R * | | | * R * |
+---*D Q*--+ | +---*D Q*--+
* * | * *
* _* | * _*
+---*CLK Q*O------+ +---*CLK Q*O
| * * | * *
| *********** | ***********
| |
| |
| |
SET RESET

Thanks, Tom! It's all coming back to me now.

...Jim Thompson
 
M

mike

Jan 1, 1970
0
Tom said:
With 2 flip flops, or with 8 NAND gates. Replace them with NORs and
swap the outputs for negative edge trigger.

OUT
|
|
+-------|--------------------------+
| | |
| | +-------------+ |
| | | | |
^ | | | ^ | |
| *********** | | | *********** |
| * R * | | | * R * |
+---*D Q*--+ | +---*D Q*--+
* * | * *
* _* | * _*
+---*CLK Q*O------+ +---*CLK Q*O
| * * | * *
| *********** | ***********
| |
| |
| |
SET RESET


I don't think you want to do that with flip-flops. Too many
race issues with clocking and resetting at the same time.
If you rewire the flops into a Johnson counter configuration,
each flip-flop has to contend only with it's own metastability
issues. One clock makes the outputs the same, the other
makes 'em different. Decode the state with an XOR.

The stuff below looks a lot like a MC4044 Phase Detector.
mike
I traced the circuit below with 4 possible initial states.

below: Q(initially) = 0 RESET = 0


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \6 +--| | /7x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| /5 | |
|NAND>-----+ |
\4 +-------| +--| Q
| |NAND>--+------- /3
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- \4
/3 +-------| +--|
|NAND>--+ \4x |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 0 RESET = 1


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \6 +--| | /7x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| /5 | |
|NAND>-----+ |
\4 +-------| +--| Q
| |NAND>--+------- /3
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- \4
/3 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 0


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \2 +--| | /3x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =0 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+--+ |
+-------| +--| |
=0 | |NAND>--+ =1
RESET -----+------------------------|


below: Q(initially) = 1 RESET = 1


/1
SET -----+------------------------|
| |NAND>--+ \2
+-------| \2 +--| | /3x
|NAND>--+-----+ |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =1 | |
|NAND>-----+ |
=0 +-------| +--| Q
| |NAND>--+------- =1
+--------------------------------+--| |
| |
+----------|--+
| |
+----------+ |
| | _
+--------------------------------+--| | Q
| |NAND>-----+---- =0
=1 +-------| +--|
|NAND>--+ =1 |
+--| | |
| | |
+----------|--+ |
| | |
+----------+ | |
| | |
+--| =0 | |
|NAND>-----+--+ |
+-------| +--| |
=1 | |NAND>--+ =1
RESET -----+------------------------|



--
Bunch of stuff For Sale and Wanted at the link below.
laptops and parts Test Equipment
4in/400Wout ham linear amp.
Honda CB-125S
400cc Dirt Bike 2003 miles $550
Police Scanner, Color LCD overhead projector
Tek 2465 $800, ham radio, 30pS pulser
Tektronix Concept Books, spot welding head...
http://www.geocities.com/SiliconValley/Monitor/4710/
 
K

Keith R. Williams

Jan 1, 1970
0
I don't think you want to do that with flip-flops. Too many
race issues with clocking and resetting at the same time.
If you rewire the flops into a Johnson counter configuration,
each flip-flop has to contend only with it's own metastability
issues. One clock makes the outputs the same, the other
makes 'em different. Decode the state with an XOR.

Hadn't thought of that! It's a much cleaner solution and purely
synchronous. Something like:

+---------------------------+ __
| +----------------|---------|<>|
| | | | |-----o Out
| | +---------|__|
| .---. | .---. |
+---|D |--+ +------|D |--+
| | | | |
R o------------->Ck |o----+ +--->Ck |o
'---' | '---'
|
S o--------------------------+
 
J

James Meyer

Jan 1, 1970
0
Does it get rid of metastability too? ;-)

I find that the more I drink, the stabler I get. Sometimes I get so
stable I can hardly stand up.

Jim (Burp) Meyer
 
K

Keith R. Williams

Jan 1, 1970
0
I find that the more I drink, the stabler I get. Sometimes I get so
stable I can hardly stand up.

Sometimes I'm (meta) stable on the bar stool. I could fall into
the potential well on the right, or the left (both stable
conditions). ...but I'm (meta) stable sitting on the local
maximum inbetween.
 
S

Stepan Novotill

Jan 1, 1970
0
This will also work in many cases,
It eliminates loss of state when both inputs go LOW.
(Use NOR if required)

Stepan

+-------| |-------|
|NAND>--+-----+ |NAND>--+-----
+--| | +--| |
| | | |
+----------|--+ +----------|--+
| | | |
+----------+ | +----------+ |
| | | |
+--| =0 | +--| =0 |
|NAND>-----+--+ |NAND>-----+--
+-------| |-------|
 
T

Tom Del Rosso

Jan 1, 1970
0
mike said:
I don't think you want to do that with flip-flops. Too many
race issues with clocking and resetting at the same time.
If you rewire the flops into a Johnson counter configuration,
each flip-flop has to contend only with it's own metastability
issues. One clock makes the outputs the same, the other
makes 'em different. Decode the state with an XOR.

That's very neat.
The stuff below looks a lot like a MC4044 Phase Detector.

It looks similar, although I derived it. Robert came up with the same
circuit in response to the same problem.
 
T

Tom Del Rosso

Jan 1, 1970
0
Jim said:
I just invented a method that avoids the "delay-game"... I'll post it
tomorrow... it's time now for Cab/Merlot blend and a filet ;-)

Where is that Jim?
 
F

Fred Bloggs

Jan 1, 1970
0
Jim said:
ISTR that there was recently a discussion of how to make an
Edge-Triggered S-R Flip-Flop... a rising edge on one input sets the
flop, a rising edge on the other input resets.

This is identical to a version of JK-FF phase detector specialized for
PLL application and used in the 74HC297 ADPLL manu'd by TI still. You
might take a look at the gate level for that. The J and K inputs are
edge clocked and set/reset the FF.
 
J

Jim Thompson

Jan 1, 1970
0
That's very neat.


It looks similar, although I derived it. Robert came up with the same
circuit in response to the same problem.

Ah, yes! MC4044, I remember it well... I described what an ideal
edge-matching phase detector would do and Ron Treadway conceived the
logic... first day was 360 gates, second day was 90, and on the third
day it was NINE! Then I designed and coined the phrase "charge-pump".

...Jim Thompson
 
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