Eagle CAM foo

[Robert Baer]

OK, start with a PCB that has some silk screen text placed in the
standard manner.
Then add a silk screen logo derived from a BMP file using
import-bmp.ulp .
Viewing the PCB with _tsilk on shows both the text and the logo.
BUT.
Doing a CAM, the resulting .plc file DOES NOT HAVE THE LOGO!!!!!!!!!!!

WTF??
How can this be fixed?

 

[Lasse Langwadt Christensen]

Den mandag den 25. november 2013 07.20.10 UTC+1 skrev Robert Baer:

OK, start with a PCB that has some silk screen text placed in the

standard manner.

Then add a silk screen logo derived from a BMP file using

import-bmp.ulp .

Viewing the PCB with _tsilk on shows both the text and the logo.

BUT.

Doing a CAM, the resulting .plc file DOES NOT HAVE THE LOGO!!!!!!!!!!!



WTF??

How can this be fixed?

check which layers the cam processsor job puts in the .plc

the standard eagle gerb274x.cam silkscreen is layers 20,21,25
so you'll need to add layer 121, _tsilk


-Lasse

 

[Uwe Hercksen]

OK, start with a PCB that has some silk screen text placed in the
standard manner.
Then add a silk screen logo derived from a BMP file using
import-bmp.ulp .
Viewing the PCB with _tsilk on shows both the text and the logo.
BUT.
Doing a CAM, the resulting .plc file DOES NOT HAVE THE LOGO!!!!!!!!!!!

Hello,

Gerber is a vector format, but it is not suitable for bitmap data.

Bye

 

[Spehro Pefhany]

Hello,

Gerber is a vector format, but it is not suitable for bitmap data.

Bye

Perhaps not the most suitable, but most of us manage to get our logos
onto our PCBs (as well as cUL etc. logos) without undue drama.


Best regards,
Spehro Pefhany

 

[Uwe Hercksen]

Perhaps not the most suitable, but most of us manage to get our logos
onto our PCBs (as well as cUL etc. logos) without undue drama.

Hello,

if there was an automatic or manual conversion from a logo in bitmap
data to Gerber vector data. I don't think the fotoplotter would handle a
mix from bitmap and vector data. Fotoplotter of these days are using
internal pixel data, but the resolution depends on the model used and
will be different from resolution of the bitmap logo.

Bye

 

[Martin Riddle]

Hello,

if there was an automatic or manual conversion from a logo in bitmap
data to Gerber vector data. I don't think the fotoplotter would handle a
mix from bitmap and vector data. Fotoplotter of these days are using
internal pixel data, but the resolution depends on the model used and
will be different from resolution of the bitmap logo.

Bye

The UL (eg UR) logos and mfg logo the board makers put on the boards
look pretty good. They are small and have some detail to them.
I don't know if they are massaged at all, but it does not look to be a
problem.

Cheers

 

[Robert Baer]

Den mandag den 25. november 2013 07.20.10 UTC+1 skrev Robert Baer:


check which layers the cam processsor job puts in the .plc

the standard eagle gerb274x.cam silkscreen is layers 20,21,25
so you'll need to add layer 121, _tsilk


-Lasse

Layer 121, _tsilk is exactly what i used for the text and the logo;
the CAM processor tab that generates the .plc file had layer 121 enabled.

I have done further investigation on this mess.
Matters not what layer one uses (1, 2, 121, 200etc).
Drawing a WIRE, it gets transferred by CAM down to 0.05mil (what
Eagle calls zero).
BUT....drawing a RECT, if the width or the length (ie one of its
dimensions) is less than 1.0mil, it gets dropped.
So, the Cam processor is flawed.
Is there a fix?

 

[Robert Baer]

Hello,

Gerber is a vector format, but it is not suitable for bitmap data.

Bye

No shit, dick tracy, that is what the ULP does..converts from BMP to
a number of RECTangles (ie: vectors).

 

[Robert Baer]

Perhaps not the most suitable, but most of us manage to get our logos
onto our PCBs (as well as cUL etc. logos) without undue drama.


Best regards,
Spehro Pefhany

And pray tell,how does the detail get transferred if BMP source?

 

[Robert Baer]

The UL (eg UR) logos and mfg logo the board makers put on the boards
look pretty good. They are small and have some detail to them.
I don't know if they are massaged at all, but it does not look to be a
problem.

Cheers

Yeah; nobody is talking as how they got pasted (pun intended) on.
If, say, they use Eagle and take the original logo to BMP converted
by ULP to SCRipt to RECTangles.
Or they use some other board program (Ivex WinBoard, etc).
Or they have a secret way of taking a vector version of their logo
and converting to Gerber (which then would not show in Eagle).
Or....

 

[Robert Baer]

I have done further investigation on this mess.
Matters not what layer one uses (1, 2, 121, 200etc).
Drawing a WIRE, it gets transferred by CAM down to 0.05mil (what
Eagle calls zero).
BUT....drawing a RECT, if the width or the length (ie one of its
dimensions) is less than 1.0mil, it gets dropped.
So, the Cam processor is flawed.
Is there a fix?

 

[Spehro Pefhany]

And pray tell,how does the detail get transferred if BMP source?

Sorry, you'd have to consult the documentation (or google for no-doubt
copious results) for your particular program- I don't use Eagle.

Hey, for my next startup I'm going to commission a logo that can be
produced by multiple layers on a PCB (eg. copper + mask + overlay).
(with due attention paid to the registration limitations of the
overlay layer). Should be fun.

--sp


Best regards,
Spehro Pefhany

 

[Uwe Hercksen]

I have done further investigation on this mess.
Matters not what layer one uses (1, 2, 121, 200etc).
Drawing a WIRE, it gets transferred by CAM down to 0.05mil (what Eagle
calls zero).
BUT....drawing a RECT, if the width or the length (ie one of its
dimensions) is less than 1.0mil, it gets dropped.
So, the Cam processor is flawed.
Is there a fix?

Hello,

there are modern fotoplotters with fine pixel resolution, they may plot
traces with a width of 1.0 mil. But this does not guarantee that these
traces may be etched on a copper layer or printed with silk screen.
Look for the smallest structures your pcb manufacturer is able to
produce on copper or silk screen.

Bye

 

[Spehro Pefhany]

Hello,

there are modern fotoplotters with fine pixel resolution, they may plot
traces with a width of 1.0 mil. But this does not guarantee that these
traces may be etched on a copper layer or printed with silk screen.
Look for the smallest structures your pcb manufacturer is able to
produce on copper or silk screen.

Bye

Hi, Uwe:-

That's an overly pessimistic interpretation. The resolution that the
supplier can typically reproduce is probably several times higher than
the guaranteed no-breaks, no-shorts line-space minimum specification.

IOW imagine a 1mm square- you might be able to reproduce a 50 or 100um
square "pixel" stuck in the middle of one side, but that doesn't mean
that the supplier guarantees that a 50mm long trace 100um wide or
traces spaced 100um apart will be electrically perfect.

Unless you want your beautiful corporate logo to come out all
pixely-like (I suppose it might be blocky to begin with), it's best to
err on the side of higher resolution. Maybe 200-300 DPI in the final
size, which is around about 80-120um.

In the old days of computing, a high-res logo could actually slow down
the layout software noticably, so one would tend to add it last, or
turn it off during significant edits. Now that everyone has fast
workstations, it doesn't seem to be noticable.

--sp

 

[Uwe Hercksen]

Unless you want your beautiful corporate logo to come out all
pixely-like (I suppose it might be blocky to begin with), it's best to
err on the side of higher resolution. Maybe 200-300 DPI in the final
size, which is around about 80-120um.

Hello,

I agree with 80 to 120 µm, but Robert Baer wrote about 1 mil or 25 µm.

Bye

 

[Robert Baer]

Hello,

I agree with 80 to 120 µm, but Robert Baer wrote about 1 mil or 25 µm.

Bye

Back in the "good old daze" of TAPING a layout, homebrew fo
double-sided (not PTH unless one was VERY brave),i would on occasion,
repeatedly do 2mil, and 1mil was iffiy.
As you may know, chemical purity, cleanliness, and techniques have
improved slightly.

BYE

 

[Spehro Pefhany]

Back in the "good old daze" of TAPING a layout, homebrew fo
double-sided (not PTH unless one was VERY brave),i would on occasion,
repeatedly do 2mil, and 1mil was iffiy.
As you may know, chemical purity, cleanliness, and techniques have
improved slightly.

BYE

I never got much better than 15 mil feature size reliably with garage
etching. You must be very talented to get 2 mil lines and spaces- more
talented than many of the Asian PCB houses that offer 6 mils as
standard and 4 mils at extra cost.

Of course if you're talking about millimeters rather than units of
0.001", that's somewhat easier. ;-)

--sp


Best regards,
Spehro Pefhany

 

[Robert Baer]

I never got much better than 15 mil feature size reliably with garage
etching. You must be very talented to get 2 mil lines and spaces- more
talented than many of the Asian PCB houses that offer 6 mils as
standard and 4 mils at extra cost.

Of course if you're talking about millimeters rather than units of
0.001", that's somewhat easier. ;-)

--sp


Best regards,
Spehro Pefhany

Ahh.. it was mils for the lines, but the smallest spacing was then in
the region of 20 mils.
I think that "pollution" from used etchant was the limiting factor.

 

[josephkk]

Back in the "good old daze" of TAPING a layout, homebrew fo
double-sided (not PTH unless one was VERY brave),i would on occasion,
repeatedly do 2mil, and 1mil was iffiy.
As you may know, chemical purity, cleanliness, and techniques have
improved slightly.

BYE

Wow, getting the tape which was usually 3 mils thick minimum to stand up
cleanly at 2 mils width is impressive. Or is there some confusion in the
units?

?-)

 

[Spehro Pefhany]

Wow, getting the tape which was usually 3 mils thick minimum to stand up
cleanly at 2 mils width is impressive. Or is there some confusion in the
units?

?-)

We used to reduce it 2:1, I imagine some fine stuff would have been
done 4:1.

Made it difficult to check the footprints.


Best regards,
Spehro Pefhany