Drift issue in capacitance measurement, why?

[Chengjun Li]

Hi everyone,
Please be patient allowing me to introduce the problem shortly.

I bought an evaluation board from a Japanese company recently. The board is used to measure very small capacitance difference by transfer input capacitance difference to output voltage, the resolution can reach 0.1fF. The board has three channels (X,Y,Z), and it can measure three capacitor pairs at the same time.

The working principle of the evaluation board is a Capacitance/Voltage conversion circuit shown below(X channel as an example).



SI terminal maintains at 2.5V. XP and XN are powered by square wave. Initially, XP is connected to 5V, XN is connected to GND, S is turned on, Cp and Cn are charged. Then, XP switched to GND, XN switched to 5V, at the same time, S is turned off. This way, the difference charges stored on Cp and Cn are transferred to CFB, the voltage across CFB is

V = (Cp – Cn) *5 / CFB


In the actual board, the circuit is added with a bootstrapping structure.



The board also has some internal registers which can adjust the gain, offset and compensate for temperature change.


To test the board, I first connected the board to no external capacitor and measured the output voltage over a certain period of time( I only use X and Y channel). I found the output voltage is always stable over several hours.



Then, I connected the board to dummy capacitor pairs(capacitance of each capacitor is around 10pF).



The day I soldered the dummy capacitor on the board, the result I got is not stable.



I changed nothing and tested it again in the next day, the result became stable.



The third day the result is also stable.


Although I don’t know why the result in the first day is not stable, I think the board works fine based on the day 2 and day 3 results.


The next test I did is to connect the board to a DIP socket using copper wire, and placed the dummy capacitor on the socket(Capacitor only connected to X channel this time, Y channel connects nothing).




I placed the setup in an oven in order to have a stable environment and connected the oven to ground to make it serve like a faraday cage.



The results I got for three times test are very bad.









I don’t know what happened? I would be very grateful if anyone could give me some suggestion?


One thing I think I need to mention is the bad result seems have no laws, but sometimes I got the result with period. Like shown below.

 

[Bluejets]

Start by putting details of the board here so others can see the specs.
At least a link to the board specs.
Otherwise the best others can do is a wild guess.

 

[Chengjun Li]

Start by putting details of the board here so others can see the specs.
At least a link to the board specs.
Otherwise the best others can do is a wild guess.

Thanks for the advisement.

The link to the board specs is http://www.actlsi.co.jp/pdf/at1006_manual.pdf#zoom=75

The manual was written by Japanese, they don't have English version. I use Google translate to understand some important information.

 

[73's de Edd]

.


Sir Chengjun Li . . . . . . .

I would certainly have suspected a stability when you used the controlled environmental chamber.

Could you enact the same testing while utilizing "sets" of:

1 . . . . . N750 type ceramic capacitors
2 . . . . . NPO type ceramic capacitors
3 . . . . . Variable air dielectric capacitors . . . .set to a common and shared value.
4 . . . . . Dipped silver mica capacitors



73's de Edd


.

 

[Sunnysky]

The SiS pins from the Op Amp are intended for "active guarding of the common signal path. WHen used asa low imoedance shield to shunt stray noise, but being at the same voltage and unity gain signal it's effective shield with any dielectric between will add no capacitance since the "guard" provides a null differential signal.

Since your photo's use no guarding, some exposure to noise is more likely.

The purpose of this card is to use two very stable capacitive sensors and monitor a tiny differential change .. I would surmise the dielectric to be tested should not be general purpose ceramic. It could be used for biological experiments or biochemical as long as they have no polar or bias or microphonic or thermal differentials or dielectric absorption, unless these abhorations were the subject of interest.

 

[Chengjun Li]

.


Sir Chengjun Li . . . . . . .

I would certainly have suspected a stability when you used the controlled environmental chamber.

Could you enact the same testing while utilizing "sets" of:

1 . . . . . N750 type ceramic capacitors
2 . . . . . NPO type ceramic capacitors
3 . . . . . Variable air dielectric capacitors . . . .set to a common and shared value.
4 . . . . . Dipped silver mica capacitors



73's de Edd


.

Thanks for your reply.

I will do the test as you suggest and update the result.

I think one thing I need to mention is yesterday I did another test with the socket soldered on board through copper wire but without external capacitors.

The result is not stable, either. Now I am suspecting that other than the capacitors, there might be other factors influence the result. Any further suggestion is welcomed.

By the way, "I would certainly have suspected a stability when you used the controlled environmental chamber." so you think a chamber can't provide a stable environment? why?

 

[Chengjun Li]

The SiS pins from the Op Amp are intended for "active guarding of the common signal path. WHen used asa low imoedance shield to shunt stray noise, but being at the same voltage and unity gain signal it's effective shield with any dielectric between will add no capacitance since the "guard" provides a null differential signal.

Since your photo's use no guarding, some exposure to noise is more likely.

The purpose of this card is to use two very stable capacitive sensors and monitor a tiny differential change .. I would surmise the dielectric to be tested should not be general purpose ceramic. It could be used for biological experiments or biochemical as long as they have no polar or bias or microphonic or thermal differentials or dielectric absorption, unless these abhorations were the subject of interest.

I actually realized that I connect the SIS terminal to nothing,that may cause some problem, but using the external capacitors, I don't know where the SIS terminal should be connected to. That's why I surrounded the whole setup with a faraday cage in my experiment. I hope this cage can replace the function of SIS.

And you are absolutely correct, the dielectric to be tested is not general purpose ceramic. This board is specifically to be used to test MEMS device(Micro electrical mechanical system). In the MEMS device, we have a parallel plate displacement sensor.

The material of parallel plate is doped silicon and dielectric material is air or vacuum.
We have such a device, and I connect it with the evaluation board, still I observe the drift issue. So I want to use dummy capacitors to do the same test, I thought the dummy capacitor won't contribute to the drift.

I think I need to mention one more test I did. I soldered the socket on board through copper wire but without external capacitors.

The result is not stable, either.

Do you think no guarding is the reason of this drift even without capacitors?

 

[Sunnysky]

The SiS pins from the Op Amp are intended for "active guarding of the common signal path. WHen used asa low imoedance shield to shunt stray noise, but being at the same voltage and unity gain signal it's effective shield with any dielectric between will add no capacitance since the "guard" provides a null differential signal.

Since your photo's use no guarding, some exposure to noise is more likely..

Normally the guard signal out from Op Amp are used to shield the input wires (common to both caps such as magnet wire twisted around each as a pair, unterminated.. This ought to reduce sensitivity to stray noise and stray capacitance changes Please Note this and scope the Op Amp output.

 

[Sunnysky]

• 
  
• The noise and drift are separate issues unless there is large CM stray e-field getting rectified asymmetrically by the integrator.
• The drift may come from any source.
• You can start with a heat gun and cold spray to check for drift due to Input offset current sensitivity, which ought to be very good by design.
• Then supply sensitivity.
• Then stray capacitance sensitivity by monitoring integrator output on scope and touch ground, CM signal , move hand around fixture... etc to determine effects of stray coupling and need for shield over DUT if necessary.
• Then check for change in RH which for air changes dielectric constant so breathing into open input terminals may be detected from differential C from %Rh
• then check for vibration sensitivity by vibrating fixture and monitor integrator output.
• then check Cp, Cn signals on scope for ringing using zero scope gnd length with tip/barrel, and clip removed. Verify S/H occurs after settling by probing cct board switch to Cfb.
• then check for Seebeck effects of intermetallic joints to see if uV ossfet of tin plate vs gold plate or nickle plate contacts on fixture has an effect.

This is just a start

Order silver Mica caps in the value same as DUT in fixture for stability tests. Keep leads short and use twisted pairs using SiS guard for shield.

If you need shields, consider Techetch or make your own out of tinned brass etched using acid and tinning solution with double sided artwork solid for cuts and solid/dotted for folds or half etch , which some board shops can do. We did this for RF proto shields over ceramic hybrids in the 90's.

MEMS ground plane could be the SiS guard signal with care on adjacent noise

 

[73's de Edd]

By the way, "I would certainly have suspected a stability when you used the controlled environmental chamber." so you think a chamber can't provide a stable environment? why?

You must have misread . . . I said that of all of the test conditions . . . .I thought the environmental chamber WOULD have produced the best results.



73's de Edd

 

[Sunnysky]

By the way, "I would certainly have suspected a stability when you used the controlled environmental chamber." so you think a chamber can't provide a stable environment? why?

You must have misread . . . I said that of all of the test conditions . . . .I thought the environmental chamber WOULD have produced the best results.



73's de Edd

Only if other EMC conditons do not exist or other factors. such as %RH or supply sensitivity or .... interface cables , inject noise into chamber or may act as bi-directional antenna with no choke or signal isolation to CM noise.


Still waiting for value of Cfb to know how many milli/pico Amps we are dealing with here.

 

[Sunnysky]

I am able to translate all of the ACT EVAL manual. The one you have now is obsolete and replaced with an improved one. In order to use this board properly, keep in mind the Cin limits on the board is very small such as 17 pF on yours with an offset range of 0.3pF and 150V/pF max sensitivity. There is an on board thermistor and registers in EEPROM for gain, offset and temp correction factors for each of the MEMS X,Y,Z accelerometers as well as Butterworth filter adjustments and 800 kHz S/H clock rate.

Their new board is capable of 5 pF max and 0.02pF delta C

Do you need expert help? , then consult an expert, if you have a budget and urgent need.

Have scope, can travel.

good luck

Tony Stewart
EE since 1975

 

[Chengjun Li]

I am able to translate all of the ACT EVAL manual. The one you have now is obsolete and replaced with an improved one. In order to use this board properly, keep in mind the Cin limits on the board is very small such as 17 pF on yours with an offset range of 0.3pF and 150V/pF max sensitivity. There is an on board thermistor and registers in EEPROM for gain, offset and temp correction factors for each of the MEMS X,Y,Z accelerometers as well as Butterworth filter adjustments and 800 kHz S/H clock rate.

Their new board is capable of 5 pF max and 0.02pF delta C

Do you need expert help? , then consult an expert, if you have a budget and urgent need.

Have scope, can travel.

good luck

Tony Stewart
EE since 1975

Thanks a lot for your reply and your precious time. I am still not clear about several things you mentioned.

"use twisted pairs using SiS guard for shield"
I am not sure how to do this. Do you mean something like what's shown below?(I know the leads need to be shorten,here I just want to figure out how to achieve air twisted magnet wire shield)


"Their new board is capable of 5 pF max and 0.02pF delta C"
I think you mean AT1027, this one is a accelerometer which has a build-in MEMS device, there is no connector on this board to connect external device. That why I use AT1006 which allow me to connect and test my own MEMS device.

"keep in mind the Cin limits on the board is very small such as 17 pF on yours with an offset range of 0.3pF and 150V/pF max sensitivity."

I am not sure about these two parameters in the manual, Csns and delta C. Does Csns mean either Cp or Cn can't be larger than 17pF? If it is then, my MEMS device should be fine whose Cp and Cn are around 10pF. Does delta C mean Cp-Cn must be smaller than 0.3pF? I think my MEMS device meets this requirement, even if it doesn't , I think I can connect a dummy capacitor in parallel with Cp or Cn to reduce the delta C.

In order the have max sensitivity 150V/pF, the several gain registers must be set the max value, like SF{X,Y}= FFH, SFTC{X,Y} = 7FH, and GAIN = 7FH. Here my setting are SF{X,Y}=FFH, GAIN= 7FH, but SFTC{X,Y}=00, so the gain is not max gain. All the other registers are set 00H.

• if 150V/pF is correct then 1 V drift = 0.0067 pF , which is programmable

What do you mean by programmable? The resolution can be 0.1fF, 0.0067pF=67fF is 670 times of the resolution which is too large to be accepted.

• You can start with a heat gun and cold spray to check for drift due to Input offset current sensitivity, which ought to be very good by design.
• Then supply sensitivity.
• Then stray capacitance sensitivity by monitoring integrator output on scope and touch ground, CM signal ,move hand around fixture... etc to determine effects of stray coupling and need for shield over DUT if necessary.
• Then check for change in RH which for air changes dielectric constant so breathing into open input terminals may be detected from differential C from %Rh
• then check for vibration sensitivity by vibrating fixture and monitor integrator output.
• then check Cp, Cn signals on scope for ringing using zero scope gnd length with tip/barrel, and clip removed. Verify S/H occurs after settling by probing cct board switch to Cfb.
• then check for Seebeck effects of intermetallic joints to see if uV ossfet of tin plate vs gold plate or nickle plate contacts on fixture has an effect.

When I connect the board to no external capacitors(just has air and the cct board dielectric between P&N), I can always get stable result.
When I connect the board to socket through copper wires but without adding external capacitor like mentioned above, I can't get stable result.
By comparing these two experiments, Can we eliminate some of the factors you mentioned above, like supply sensitivity, if the problem lie in the power supply, then I think I shouldn't get stable result in the first experiment.

Looking forward to your reply.

Thanks.
Chengjun Li

 

[Sunnysky]

It seems the micromotion of the socket is a major source of drift errors. So eliminate it.

Perhaps Swiss style circular sockets will be more stable with fixed outer socket and circular spring contact inside rather than parallel contacts in IC socket which can move, while soldered connections are best.

To verify drift, apply static force on socket and see how sensitive it is , while observing output on S/H like CLYO (cap load Y out). Find all the locations and sensitivty to shift by applying pressure on board with non metallic tool, shift proximity of cables, move hand/finger near board.

I see user blank perf area on EVAL board beside interface holes on board, so why not use that.

Maybe use Swiss style socket or other rigid connectors with magnet-wire for neat short wires (1cm) to socket on EVAL board. Move wires or Twist board gently to test for sensitivity and need for improved connections. Remember sockets and wires moving will act like MEMS cap. The outer conductors, control the sensitivity to differential motion, While SIS provides a virtual AC ground to the SI signal.

So you may see sockets are a bad idea for measuring fento-farads

I recall when using XYZ accelerometer in the 70's, moving the coax to sensors shifted the output several g's so every cable had to be restrained from motion.

Since SI (sig. in) is the common mode point from each sensor from which all xyz measurements are made, the SIS .(sig. in shield) buffers the input to apply the same voltage around the SI path so there is no voltage difference and any capacitance between these will draw no current from SI since dv/dt is =0 Thus must be true up to 1MHz so , it is ok to tightly wind a magnet wire a few turns around per cm as long as the turns are rigid so dC/dt does not induce dv/dt noise.

This will reduce effects of stray capacitance to common perf board dielectric outside SiS as SiS is closest to SI and low impedance compared to SI and adjacent material. The SiS guard signal pair is generally tightly twisted around signal and is characterized as controlled impedance transmission line in the rang of 100-200Ω with an added capacitance of ~0.5pF/cm. vs unshielded which raises impedance to ingress noise from stray inductance and capacitance

So use less air gap and wrap tight enough to prevent microphonics.

The C0G cap you have is ok at 10pF matched to 1% is good for stability tests as long as it void of micro motion.

I did not calc. your gain but you might figure how to do this from full scale fF and ADC resolution.

 

[Sunnysky]

it appears to me your gain is max but temp compensation is 0

. like SF{X,Y}= FFH, SFTC{X,Y} = 7FH, and GAIN = 7FH.
my setting are SF{X,Y}=FFH, GAIN= 7FH, but SFTC{X,Y}=00, so the gain is not max gain. All the other registers are set 00H.