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DIY PC Oscilloscope

Discussion in 'Electronic Design' started by [email protected], Mar 9, 2013.

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  1. Guest

    Hi all,
    I've started designing a 200 MSPS Oscilloscope with a 25 MHz analog bandwidth, 3Ksample/channel buffer.
    The oscilloscope can be connected to a PC via USB, and eventually via Ethernet and WiFi.
    The trigger is ( at moment) rising, falling... auto, normal.

    I would appreciate suggestions and or comment for possible improvement and functionality that could make this oscilloscope interesting.

    Thanks,
    Francesco
     
  2. In theory is possible to have a 5 ns p-p trigger jitter, but only when the noise floor is less then 0.5 LSB, otherwise you need to add some form of histeresys that will increase the jitter opening. but in theory is possible
    I'm using an FPGA for triggering and buffer. at moment a small device, as I'm quite impressed with the results (tomorrow I will post a video on my blog) next revision I'm planning a SPartan 6 with external memory IF.
    Correct, I have spend 2 months or maybe 3 just to design the analog parts, I must admit I believe I have over designed, but i'm very happy with the results so far. My plan is to measure and publish the analog bandwidth.
    The scope has a compensated attenuation in the front end that seems doing agood job. Therefore there is not needed for SW tricks. I personally don't like
    I think the Picoscope 200 series is the main competitor, which is around 200£ + VAT
     
  3. Tim Williams

    Tim Williams Guest

    Why only 25MHz? Yes it's easier, but the ADC probably has an analog
    bandwidth in the GHz. Why waste it?

    My TDS460 has 100MSa/s and 350MHz bandwidth. For periodic signals, it's
    as good as an off-the-shelf MSO or DPO series (arguably better since it
    doesn't have that retarded DPO crap you can't turn off), which usually
    claim something ignorant like 5GSa/s and a mere 100MHz.

    As John says, the attenuator is the hard part. Perhaps you could pilfer
    them from old analog or digital scopes, and feed the output to your ADC
    and trigger generator.

    Tim
     
  4. Thanks Tim,
    good point,
    Actually in theory I could use the DLL inside the FPGA and changing the clock phase with a resolution of 25 ps... so in theory I have a 1 GSPS FPGA for repetitive signals!
    Do you think it would make more attractive to buy?
    Actually the maximum bandwidth is 70 MHz, I'm low filtering for aliasing.
     
  5. Thnanks Jeff,
    I like the idea of the Cable that stop "unwanted borrowed" I will actually do this... not sure about the camera on probe :)...

    I may add a block diagram ( notthe full schematic) to show people how to calibrate the scope and some test points and hits to help people to self repair the scope.

    also the function generator, could be a good sales point

    Thanks
     
  6. Tim Williams

    Tim Williams Guest

    Nah, 25ps resolution means you can take acquisitions shifted in time every
    25ps -- 40GSPS equivalent! But, do beware of the manufacture and
    temperature variation of the delay. FPGAs are made for worst-case timing
    constraints, and anything that's adjustable (like a DLL) is put inside a
    loop (hence, DL*L*).
    Heck, make it better than a Rigol, from cheaper parts. And open source it
    (if it's that kind of project). Create shock waves in the marketplace!
    ;-)
    My TDS460 says "50GS/s ET" (Equivalent Time) on 1ns/div. Looks like it's
    actually filling the whole screen with that resolution, not just
    interpolating between samples.

    The 100MHz, ~10MS/s HP54600B goes down to 1 or 2ns/div or something like
    that, but it uses sinc interpolation on such fine scales. I don't know
    what a Rigol does for high sampling rates.

    If you skip antialiasing filters, you get sharper displays and equivalent
    time sampling. If you filter, you're basically saying: "Yep, I purchased
    this 200MS/s ADC, and the FPGA to run it, and I'm taking both of them over
    to the grinder and shaving off... ohh about 80% of the silicon, because...
    I like the smell?"

    Filtering basically negates the trigger generator, too. You could sample
    continuously and do the trigger digitally instead. Which...

    ....I think for any particular period between trigger crossings, you'd want
    to use some sort of interpolation to adjust the timing -- sample N is a
    bit below the threshold, and sample N+1 crossed the threshold by so-and-so
    and caused a trigger, so we know the dV/dt and can estimate where it *did*
    actually cross. So we can stack this sample period on top of the other,
    which crossed at whatever rate, by aligning it. Shift everything sideways
    by the calculated time difference, using a suitable interpolation (a
    simple quadratic spline would be reasonable, but a sinc interpolation
    might be more physically significant), then stack it up for display.

    The "stacking" itself could be an array of buffers (so you have a memory
    of many traces, and can perform statistics on them to generate the
    display -- decimate (view only one), average (which would now be a FIR
    "sliding average", which AFAIK, no scope manufacturer ever does for
    averaging mode!), peak detect, median, RMS + std dev., etc. This display
    process could, of course, be done for either acquisition method
    (continuous or triggered).

    But again, such hackery, though interesting, doesn't get your bandwidth
    back, it's just software diddling for not being clever enough to get the
    bandwidth and trigger right in the first place. :)

    Tim
     
  7. Guest

    the first thing I would add is USB isolation (data and power) so that
    when using usb and/or
    powering it from usb the scope is isolated from the pc

    -Lasse
     
  8. Good point,
    I was thinking to use an ADuM5xxxx from AD.
     
  9. I get the point... and your are not the first one to tell me that.
    but I believe that an oscilloscope is still an instruments a lot of electronic enthusiastic would love to have it if priced correctly.
    Marketing will be the biggest challenge in a market so competitive.
     
  10. Nico Coesel

    Nico Coesel Guest

    Did you look what a Siglent scope costs on Ebay? IIRC its about US
    $180 including shipping from China. How do you expect to beat that?
    BTW Lecroy sells the exact same scope for a lot more.
     
  11. Jamie

    Jamie Guest

    Yeah, but it has Lecroy's name on it and that's like GOLD!!!!!!!!!!!

    :)
    Jamie
     
  12. I've wanted to make something like a "dynamic signal analyser" that goes
    up to 1 or 10 MHz, instead of 100kHz like they all seem to.

    High dynamic range (16+ bit) low noise, with arb generator.

    I've got one of these, and I like it, but it is a big old slow beast of
    a thing:

    <http://www.teknetelectronics.com/Search.asp?p_ID=13689&pDo=DETAIL>
     
  13. it's challenging but not impossible.
    I agree...It is very difficult to compete with China, but not impossible if we point on quality.
     
  14. Nico Coesel

    Nico Coesel Guest

    If you think the Chinese can't make quality stuff then you've made
    your first big mistake. If its good enough for Lecroy to stick their
    badge on the quality bit is in order.

    So re-think your competitive edge. Remember that a good DSO is 5%
    hardware and 95% software. So even if you get the hardware right you
    are still nowhere near a sellable product.
     
  15. From my (rather narrow) point of view, where the main use of an
    oscilloscope is in debugging embedded software, this would make it
    stand out above the competition.
     
  16. Thanks Roberto,
    I'm not sure what do you mean with a stackable oscilloscope, do you mean... e.g. 4 oscilloscopes... 2 channel each that makes a 8 channel oscilloscope?
    The only problem I see with that is that between each scope you can have 20 ns max. of time offset.
     
  17. hamilton

    hamilton Guest

    Wouldn't it be easier to pass the trigger between modules ??

    Getting one signal right would be easier then getting 4-8-12 signals right.

    My $0.02
     
  18. That is what I understood from Jeff's post.
    That could be unacceptable in some scenarios, and not important at all
    in others. May be you can add a common clock or some other HW trick to
    synchronize several units?
     
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