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divide by 25/16

Discussion in 'Electronic Design' started by colin, Aug 14, 2006.

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  1. colin

    colin Guest

    Hi,
    I need a circuit to divide a <50mhz digital signal by 25/16.
    ie. i need to lose 9 out of every 25 pulses.
    Is there a simple/standard way to do this ?

    Ive come up with a few ideas that use quite a lot of logic,
    such as a divide the input by 25 with 1-25 decoder wich then swallows a
    pulse at the apropriate count.

    or divide by 16 on the output wich swallows a pulse every other count and
    also at terminal count.
    but it runs into trouble becuse it swallows its own clock pulses and doesnt
    advance.

    or invert the clock input to a flip flop with an xor from its output, wich
    gives a nice looking pulse train
    but needs a few more pulses taken out.

    Its to go after a 3ghz divide by 64 prescaler so the combined divide is 100.

    Colin =^.^=
     
  2. Jim Thompson

    Jim Thompson Guest

    25/16 is unusual. Usually it's 15/16 or 7/8, etc. Surf on "dual
    modulus pre-scaler".

    ...Jim Thompson
     
  3. colin

    colin Guest

    Thanks, im familiar with dual modulus prescalers but usualy only seen them
    within PLL chips,
    I think they divide by either of the 2 ratios one of wich is 1 higher
    so that a single count can be swallowed by switching to the higher modulus.
    I found it a bit confusing when I first came accros it, you end up with
    illegal divide ratios etc.

    However I need divide by 25/16 ie 1.5625 not divide by 25 or 16. so im not
    sure they will work, unless they can replace the /64 prescaler completly.

    At the moment Im using a 3ghz PLL chip as a /100 prescaler but needs to be
    programed each time, shame /100 3ghz prescalers dont seem to be available, I
    could live with the /64 and work out the real frequency but id rather make
    it easier.

    Colin =^.^=
     
  4. Tim Wescott

    Tim Wescott Guest

  5. How about dividing by a symmetrical output factor of 25 (1.875 MHz
    output), and then use a rather modest pll to multiply that frequency
    by 16.
     
  6. colin

    colin Guest

    Although that would give the right output, it would limit the input range by
    the range of the vco and is probably a bit more complicated, idealy i just
    want to lose 9 out of every 25 input pulses, hopefully with just a few logic
    ics.

    preferably not to lose all nine one after the other but thats just me being
    a perfectionist.

    Colin =^.^=
     
  7. APR

    APR Guest

    I thing his intention is to have sixteen twentyfifths, he wants to "divide
    by 25/16" or multiply by 16/25
     
  8. I wonder if the 7497 is available in a fast enough logic family.
    http://www-s.ti.com/sc/ds/sn7497.pdf
     
  9. Jim Thompson

    Jim Thompson Guest

    I was going to suggest rate multipliers but you beat me to it.

    You might have to roll your own out of PECL.

    ...Jim Thompson
     
  10. colin

    colin Guest

    yes I want sixteen twentyfiths of the input frequency or x 0.64
    oh hey hang on but thats the same as dividing by twenty five sixteenths
    wich is divide by 1.562, so you both right.

    25/16 is just the smallest rational fraction.

    its what you need to add on to a divide by 64 prescaler to get it to a nice
    round decimal divide by 100.

    Colin =^.^=
     
  11. colin

    colin Guest

    Ah yes rate multipliers, I never realy studied their internal circuit much
    till now, they always seemed confusing.

    the 7497 doesnt seem to be available in any flavour,
    digikey has some cmos 4000 ones.

    how hard can it be to just lose 9 out of 25 pulses. 50mhz shld be doable
    with the higher speed 74 cmos families I think.

    Colin =^.^=
     
  12. Ken Smith

    Ken Smith Guest

    This will fit into a 22V10 so you can do it with one chip if you want.

    The dinner bell just rang. I'll be back with something not using
    programable parts after dinner.
     
  13. colin

    colin Guest

    heh cool enjoy dinner !
    ive managed it so far with a divide by 16 counter and a D type flipflop but
    also quite a lot of gates of different types.
    maybe I can minimise those down to use just a couple of quad gate chips.

    Colin =^.^=
     
  14. budgie

    budgie Guest

    Most swallow systems result in an irregular output waveform, which may or may
    not create downstream issues (such as unwanted sidebands/spurs). I suspect you
    have created a problem by your choice of /64. Can you not source some other
    prescaler? If not, you are probably looking at two cascaded dual modulus divide
    by 4/5 stages, and I'm not aware of any integrated 4/5 devices.
     
  15. James Waldby

    James Waldby Guest

    colin wrote:
    ....
    ....

    As 25/16 = (5/4)^2, if you follow a 5/4 divider by
    another one, you'll have 25/16.

    -jiw
     
  16. colin

    colin Guest

    oo, thats well spotted, so I need 2 circuits that each lose 1 out of 5
    pulses.
    I wonder if that actually works out simpler than 1 that loses 9 out of 25.
    or did you have something in mind ?

    Colin =^.^=
     
  17. colin

    colin Guest

     
  18. Mark

    Mark Guest

    You need to think about this carefully, as another poster mentoined,
    what you will get is an irregular pulse train, actually a signal that
    jumps back and forth beteen two frequencies that average out to your
    desired frequency but is never actually equal to your desired
    frequency. If this is OK for your application, then go for it, in many
    cases this is not OK.

    Mark
     
  19. Ken Smith

    Ken Smith Guest

    Ok I'm back from dinner :>


    If you write out the numbers from 0 to 25 in base 5, you will discover
    that the lower digit is odd 10 times. Just looking at the LSB of the
    counter, you could skip 10 clock pulses.

    When the upper digit is 4, you could allow one clock for one of the odd
    numbers


    LSB A -------------------------! \
    !NAND >------- Allow clock
    B --------------! \ --! /
    !NAND >--
    C -- -----! /
    !
    ... etc .. !
    !
    MSB H---------
     
  20. Ken Smith

    Ken Smith Guest

    Rate multipliers are easy to understand if you start with the idea of
    making a very bad one and then improve it like this.

    Given a binary counter and a binary comparitor, you can allow the clock to
    come out until the number in the counter hits some value and then block
    the count until the counter overflows.

    This gives a very bursty output.

    Now rewire the counter swapping the order of the bits so that the LSB is
    hooked to the MSB of the comparitor and so on. Observe how that spreads
    out the pulses.

    This is how I first got ahold of how they work.
     
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