Connect with us

Discrete time PID control

Discussion in 'Electronic Design' started by Andrew Holme, Jan 30, 2011.

Scroll to continue with content
  1. Andrew Holme

    Andrew Holme Guest

    I've implemented a DSSS receiver in an FPGA. The code rate NCO is
    controlled by an early/late detector. The carrier NCO is controlled by a
    Costas Loop. I chose PI gain constants for the control loops by trial and
    error but would like to do it more scientifically by analysing stability
    using a Bode plot of open loop gain. I always do it this way for analogue
    PLLs; but I'm new to z-domain stability analysis.

    TimW - I bought your book; but, to be honest, found it quite heavy going.
    Nevertheless, adapting some code from the accompanying CD, I came up with
    this Scilab script:

    kPD = 2^20;
    kP = 2^(41-64);
    kI = 2^(15-64);
    kNCO = 10000;
    G = -kPD * (kP + kI/(%z-1)) * kNCO / (%z-1);
    G.dt = 1e-3;

    The resulting Bode plot never even passes through unity gain! So is the
    system unconditionally stable? Here's a simplified version of the FPGA

    `define KP 41
    `define KI 15

    reg [63:0] phase, rate; // 64 places after the binary point
    reg signed [31:0] err; // = Early - Late

    always @ (posedge clk) // 10 MHz
    if (millisecond) begin
    phase <= phase + rate + (err << `KP);
    rate <= rate + (err << `KI);
    end else
    phase <= phase + rate;

    It clocks at 10 MHz and applies corrections every millisecond; hence dt=1e-3
    and kNCO = 10000.

    Is the Bode plot correct?

  2. Andrew Holme

    Andrew Holme Guest

    err is fine-grained: approx +/- 2^20

    Actually, kPD slope should be 2*(2^20) per chip.
  3. Andrew Holme

    Andrew Holme Guest

    Tim, thank you. I had applied that kNCO=10000 multiplier to both kI and kP.
    It should only be applied to kI for exactly the reason you have pointed out.

    The following code is giving me a sensible looking Bode plot:

    kPD = 2^20;
    kP = 2^(41-64);
    kI = 10000 * 2^(18-64);
    G = -kPD * (kP + kI/(%z-1)) / (%z-1);
    G.dt = 1e-3;

    I'm using `KI=18 in the latest FPGA. The rate was taking several seconds to

    Thanks for the free consultancy :) I will study the book.
Ask a Question
Want to reply to this thread or ask your own question?
You'll need to choose a username for the site, which only take a couple of moments (here). After that, you can post your question and our members will help you out.
Electronics Point Logo
Continue to site
Quote of the day