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Differential amplifier offset issue

Hi,
I am designing a multiple stage amplifier.
I have a first stage
differential amplifier using JFETs which gives output with a 5 volt
offset on the drain.
Now i want to amplify this signal more, i can't feed it to the
intrumentation amplifier without blocking capacitors. And i want to
avoid using blocking capacitors.
For this reason i was thinking to design another differential stage
using PNP BJTs to amplify as well as DC level shift the signal to 0
volts. Then if needed i can feed this to a instrumentation amplifier.
So currently, i am trying to design a PNP differential stage which can
take 5 volts as the base and collector around 0 volts. I have tried
some simulations in spice but can't get it working.
Can anyone help , please?
 
E

Eeyore

Jan 1, 1970
0
Hi,
I am designing a multiple stage amplifier.
I have a first stage
differential amplifier using JFETs which gives output with a 5 volt
offset on the drain.
Now i want to amplify this signal more, i can't feed it to the
intrumentation amplifier without blocking capacitors. And i want to
avoid using blocking capacitors.
For this reason i was thinking to design another differential stage
using PNP BJTs to amplify as well as DC level shift the signal to 0
volts. Then if needed i can feed this to a instrumentation amplifier.
So currently, i am trying to design a PNP differential stage which can
take 5 volts as the base and collector around 0 volts. I have tried
some simulations in spice but can't get it working.
Can anyone help , please?

That's a fairly basic amplifier. Do you have a schematic ?

Graham
 
A

Ancient_Hacker

Jan 1, 1970
0
Hi,
I am designing a multiple stage amplifier.
I have a first stage
differential amplifier using JFETs which gives output with a 5 volt
offset on the drain.
Now i want to amplify this signal more, i can't feed it to the
intrumentation amplifier without blocking capacitors. And i want to
avoid using blocking capacitors.
For this reason i was thinking to design another differential stage
using PNP BJTs to amplify as well as DC level shift the signal to 0
volts. Then if needed i can feed this to a instrumentation amplifier.
So currently, i am trying to design a PNP differential stage which can
take 5 volts as the base and collector around 0 volts. I have tried
some simulations in spice but can't get it working.
Can anyone help , please?

The simplest way is to use two resistors, say 50K and 150K in series to
-15 volts.

The center tap will be at zero volts.

You lose a little gain but what the heck.

or use a 5V zener in place of the 50K resistor, no gain lost.
 
E

Eeyore

Jan 1, 1970
0
John said:
The best place to eliminate the offset, is probably the
first stage.

I think he's referring to the 'offset' between gate and drain John.

Graham
 
J

John Popelish

Jan 1, 1970
0
Hi,
I am designing a multiple stage amplifier.
I have a first stage
differential amplifier using JFETs which gives output with a 5 volt
offset on the drain.
Now i want to amplify this signal more, i can't feed it to the
intrumentation amplifier without blocking capacitors. And i want to
avoid using blocking capacitors.
For this reason i was thinking to design another differential stage
using PNP BJTs to amplify as well as DC level shift the signal to 0
volts. Then if needed i can feed this to a instrumentation amplifier.
So currently, i am trying to design a PNP differential stage which can
take 5 volts as the base and collector around 0 volts. I have tried
some simulations in spice but can't get it working.
Can anyone help , please?

The best place to eliminate the offset, is probably the
first stage. How about showing us what you have, so far, as
a first stage. If you are using LTspice to simulate, you
can post a copy of the schematic file. Otherwise, point us
to a web page where the schematic is available, or post a
graphic in alt.binaries.schematics.electronic.
 
J

John Popelish

Jan 1, 1970
0
Eeyore said:
(snip)



I think he's referring to the 'offset' between gate and drain John.

But if it is a differential circuit with a differential
output, it wouldn't be a problem for the downstream IA,
would it?
 
I have put the schematic of the circuit on the following link:
http://img167.imageshack.us/img167/6973/diffampcd3.jpg

I am making alow noise differential transimpedance amplifier. I had to
bias the JFETs in their linear region, the bias values are shown in the
figure.
Now i have the output coming out of the drain of the cascode devices Q1
and Q2 with almost 4 volts DC.
Here i was planning to connect my PNP differential stage for DC level
shifting.
 
J

John Popelish

Jan 1, 1970
0
I have put the schematic of the circuit on the following link:
http://img167.imageshack.us/img167/6973/diffampcd3.jpg

I am making alow noise differential transimpedance amplifier. I had to
bias the JFETs in their linear region, the bias values are shown in the
figure.
Now i have the output coming out of the drain of the cascode devices Q1
and Q2 with almost 4 volts DC.
Here i was planning to connect my PNP differential stage for DC level
shifting.
If you connect the two outputs of this circuit to an
instrumentation amplifier, or other differential amplifier,
it will subtract the drain voltage of Q1 from the drain
voltage of Q2, and amplify this difference.

As long as your differential down stream amplifier includes
+4 volts in its common mode range, I don't see that you have
a problem.
 
I have put the schematic of the circuit on the following link:
http://img167.imageshack.us/img167/6973/diffampcd3.jpg

I am making alow noise differential transimpedance amplifier. I had to
bias the JFETs in their linear region, the bias values are shown in the
figure.
Now i have the output coming out of the drain of the cascode devices Q1
and Q2 with almost 4 volts DC.
Here i was planning to connect my PNP differential stage for DC level
shifting.

If you cascoded your N-FETs with P-channel FETs to created a
complementary cascode, you could lose the offset. I'd use PNP- bipolar
transistors myself, but there's no accounting for taste.
 
If you connect the two outputs of this circuit to an
instrumentation amplifier, or other differential amplifier,
it will subtract the drain voltage of Q1 from the drain
voltage of Q2, and amplify this difference.
As long as your differential down stream amplifier includes
+4 volts in its common mode range, I don't see that you have
a problem.

You are right John. It was me being stupid - i made a mistake in
connecting my preamp outputs to the IA. I just got tensed and seek help
- as this forum has been very helpful all the time.
Still i have this desire in my heart to use a PNP differential stage
right after the preamp. In terms of noise, will the PNP work better
than my IA. I don't know - but i am curious to find out that.
By the way, the IA is working fine even with a 5 volt dc offset at the
inputs:). thanks a lot guys.
 
E

Eeyore

Jan 1, 1970
0
John said:
But if it is a differential circuit with a differential
output, it wouldn't be a problem for the downstream IA,
would it?

I'm not sure he's using the term 'instrumentation amplifier' as you and I
would do. I suspect it's not differential.

Graham
 
F

Fred Bartoli

Jan 1, 1970
0
[email protected] a écrit :
I have put the schematic of the circuit on the following link:
http://img167.imageshack.us/img167/6973/diffampcd3.jpg

I am making alow noise differential transimpedance amplifier. I had to
bias the JFETs in their linear region, the bias values are shown in the
figure.
Now i have the output coming out of the drain of the cascode devices Q1
and Q2 with almost 4 volts DC.
Here i was planning to connect my PNP differential stage for DC level
shifting.

It's better to tie the Q1-Q2 gates to Q3-Q4 sources.
Q3-Q4 work with very low VDS and almost surely are biased in their
linear region (unsaturated ID). Thus your CMRR will heavily depends on
Q3-Q4 matching. Changing Q1-Q2 gates will correct this and also give you
higher input CM range.
 
E

Eeyore

Jan 1, 1970
0
Fred said:
[email protected] a écrit :

It's better to tie the Q1-Q2 gates to Q3-Q4 sources.
Q3-Q4 work with very low VDS and almost surely are biased in their
linear region (unsaturated ID). Thus your CMRR will heavily depends on
Q3-Q4 matching. Changing Q1-Q2 gates will correct this and also give you
higher input CM range.

Excellent point. I'd have done it myself that way without thinking of course
! :)

Graham
 
A

Ancient_Hacker

Jan 1, 1970
0
I have put the schematic of the circuit on the following link:
http://img167.imageshack.us/img167/6973/diffampcd3.jpg

I am making alow noise differential transimpedance amplifier. I had to
bias the JFETs in their linear region, the bias values are shown in the
figure.
Now i have the output coming out of the drain of the cascode devices Q1
and Q2 with almost 4 volts DC.
Here i was planning to connect my PNP differential stage for DC level
shifting.


You could "cheat" and look at how others have solved this problem. Try
googling for "tektronix 465 manual" or "TL084 schematic".
 
It's better to tie the Q1-Q2 gates to Q3-Q4 sources.
Q3-Q4 work with very low VDS and almost surely are biased in their
linear region (unsaturated ID). Thus your CMRR will heavily depends on
Q3-Q4 matching. Changing Q1-Q2 gates will correct this and also give you
higher input CM range.
Thanks Fred.
But i see my voltage gain drops to lees than one when i tie the Q1-Q2
gates to Q3-Q4 sources. Why is this helps to improve the CMRR - sh'ld i
get on paper and use small signals models to calculate CMRR or ther is
an easy explaination.
 
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