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difference between 7473 and 7473A

Discussion in 'General Electronics Discussion' started by silhouette, Sep 16, 2015.

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  1. silhouette

    silhouette

    3
    0
    Sep 16, 2015
    I am making a counter which counts through 0,1,2,3,5,0 using JK flip flops(7473)
    My equations are
    Jc=BA Kc=1
    Jb=C'A Kb=A
    Ja=1 Ka=B'
    Reset of all flip flops are connected to same switch and clock is common with frequency 1Hz.
    When I try this circuit with 7473 IC it works without any issues, but when I try it with 74LS73AP by Mitsubishi electrical the values of C,B and A initially toggle to 1,1,1 instead of 0,0,1 and continue giving random numbers. Could someone please explain the differences between the two and explain why I get different outputs.
     
  2. eetech00

    eetech00

    95
    8
    Nov 17, 2014
    Hi

    7473 triggers on positive edge clock, 74LS73A triggers on negative edge clock.
    Review the function tables on the data sheet.
     
  3. silhouette

    silhouette

    3
    0
    Sep 16, 2015
    I understand that 7473 triggers on positive edge of clock and 74LS73A triggers on negative edge. But my question is why it causes a difference in output in the two cases. Wouldn't the outputs be same if the flip flop is positive or negative edge triggered.
    The dottiest also state that 7473 is Master Slave flip flop. Could this be the reason for the difference in outputs
     
  4. eetech00

    eetech00

    95
    8
    Nov 17, 2014
    o_O Can you point to a datasheet so we can speak the same terminology?
    better yet post your circuit..:cool:
     
  5. silhouette

    silhouette

    3
    0
    Sep 16, 2015

    Attached Files:

  6. eetech00

    eetech00

    95
    8
    Nov 17, 2014
    Hi

    If your testing on a breadboard, I see three possible issues.
    1. Your switch doesn't include a debounce circuit. The switch contacts could bounce causing multiple logic transitions to be sensed by the logic inputs
    2. The datasheet states that the 74LS73A has a "setup" time of 20ns. This means that the logic level seen by the FF inputs must be stable for at least 20ns before the clock input transitions from high to low. Otherwise the output state is unpredictable.
    3. A 0.1uF or 0.01uFcap should be connected from each chips +V power to ground to keep power supply voltage stable. If not used, supply voltage fluctuations could cause erratic operation.

    Also, holding the CLR bar input at ground overrides the J/K/Clock inputs and sets Q bar high.
    So if the switch output is at ground on power up, all Q outputs would initially be low,
     
    Last edited: Sep 18, 2015
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