D
DFT
- Jan 1, 1970
- 0
Dear Group,
Please contact if you are interested in the DFT job listed below.
Regards,
Brent
[email protected]
Senior DFT Methodologies Engineer
Location Plano, Texas (next to Dallas)
Salary $110K- $125K
Position Description
Develop, document and implement DFT methodologies for the Structured
Digital Products Business unit
· Memory BIST Algorithm Development, Support & Documentation
· Define, support and document JTAG implementation standards and
methods
· Define, support and document DFT strategies for IP and transceivers
· Develop, support and document strategies for delay fault testing
· Define and drive DFT software tool strategy, both industry standard
and internally developed
- Interface with 3rd party vendors and CAD department
- Contribute to future software vendor selection
- Define internal/custom software & script needs and work with CAD on
implementation
· Ownership for all aspects of the DFT strategies for the Business
Units Product Lines
Position Requirements
· 3+ years in ASIC Design
· 3+ years in DFT Methodology/Implementation
· 7+ years total Industry (ASIC) Experience
· Memory BIST Algorithm development and implementation
· At-speed, Diagnostic for Failure Analysis
· JTAG Boundry Scan Design & implementation
· IC Parametric test methods and implementation
· Transition & Path delay testing
· Scan testing methods
· Low pin-count test methods
· IP test methods & implementation
· PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI
· Experience with industry standard DFT tools such as Synopsys or
Mentor (Synopsys preferred)
· Excellent written and verbal communication skills in English
· Ability to travel domestically and internationally as needed
(15-20%)
Please contact if you are interested in the DFT job listed below.
Regards,
Brent
[email protected]
Senior DFT Methodologies Engineer
Location Plano, Texas (next to Dallas)
Salary $110K- $125K
Position Description
Develop, document and implement DFT methodologies for the Structured
Digital Products Business unit
· Memory BIST Algorithm Development, Support & Documentation
· Define, support and document JTAG implementation standards and
methods
· Define, support and document DFT strategies for IP and transceivers
· Develop, support and document strategies for delay fault testing
· Define and drive DFT software tool strategy, both industry standard
and internally developed
- Interface with 3rd party vendors and CAD department
- Contribute to future software vendor selection
- Define internal/custom software & script needs and work with CAD on
implementation
· Ownership for all aspects of the DFT strategies for the Business
Units Product Lines
Position Requirements
· 3+ years in ASIC Design
· 3+ years in DFT Methodology/Implementation
· 7+ years total Industry (ASIC) Experience
· Memory BIST Algorithm development and implementation
· At-speed, Diagnostic for Failure Analysis
· JTAG Boundry Scan Design & implementation
· IC Parametric test methods and implementation
· Transition & Path delay testing
· Scan testing methods
· Low pin-count test methods
· IP test methods & implementation
· PLL, DLL, A/D, D/A, Transceivers: LVDS, PCI-e, XAUI, USB, SPI
· Experience with industry standard DFT tools such as Synopsys or
Mentor (Synopsys preferred)
· Excellent written and verbal communication skills in English
· Ability to travel domestically and internationally as needed
(15-20%)