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Designing Schmitt trigger oscillator using CMOS NAND gate.

Discussion in 'Sensors and Actuators' started by Alex_Bam, Jan 26, 2021.

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  1. Alex_Bam


    Sep 28, 2020
    I am designing a Schmitt trigger oscillator based on a CMOS NAND gate. The block diagram along with schematics and its results are attached for your reference. I am using the CADENCE tool with 0.35um technology.

    Question: it can be seen in the result, the charging time of the capacitor is large which affects the oscillating signal at the beginning. To reduce charging time I need to reduce the RC time constant but it affects my oscillating frequency. Once i reduce the RC time constant then i am limited to a certain oscillating frequency.

    Oscillating frequency: f=1/2.2RC

    How can I reduce the charging time of the cap (other than the RC time constant in my schematics) so that I get the least distortion at the initial stage of the oscillating signal?

    Attached Files:

  2. Bluejets


    Oct 5, 2014
    Charge the cap first.
  3. Harald Kapp

    Harald Kapp Moderator Moderator

    Nov 17, 2011
    You will probably not get it to start in an ideal condition. This kind of oscillator isn't very precise anyway as the frequency depends on the accuracy not only of R and C but also badly defined tolerances of the Schmitt-Trigger gate.
    Try biasing the capacitor to 1/2 Vcc by a resistive divider with very high impedance (e.g. 2 × 1 MΩ). The impedance of the divider (here 500 MΩ, 1/2 of the single resistors) needs to be much higher than the resistance of the feedback resistor to minimize influence during oscillation. Set the impedance of the divider to > 100 × Rfeedback (no clear equation, just a rule of thumb).
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