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Designing a synchronous counter (Help me please)

Discussion in 'Electronics Homework Help' started by Stebven1231, Nov 1, 2012.

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  1. Stebven1231

    Stebven1231

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    Nov 1, 2012
    My homework is to design a binary, bi-directional(up/down), preselectable, and self correcting counter from D flip-flop that counts from 0 to10 and from 10 to 0 if we change the direction of counting.

    So, there're two schematics i've found and tried to get my counter work well. I am not into in it at all and it seems far too difficult to me. So i need your help.

    Schematics "A":
    I myself could successfully get my counter to count "up" and go back to zero if the output is "1010". But that's all i could do so far.
    https://www.electronicspoint.com/attachment.php?attachmentid=6040&stc=1&d=1351812491


    Schematics "B":
    I found a datasheet of a counter IC that contains D flip flops and many gates. Here it is:
    https://www.electronicspoint.com/attachment.php?attachmentid=6038&stc=1&d=1351812067
    I then tested it with Multisim and it worked pretty well. Although I simplified it and I missed its "ripple carry output"
    https://www.electronicspoint.com/attachment.php?attachmentid=6039&stc=1&d=1351812211
    It now counts from 0 to15 and 15 to 0

    Which of the schematics would it be easier to modify? (I think it'd be schematics "B" but I am not sure how can i do this? What should I do to get it work as it should? Help me if you can. Thanks.
     

    Attached Files:

  2. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    Are you supposed to design it, or look at existing chips and copy their design?
     
  3. Laplace

    Laplace

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    Apr 4, 2010
    The assignment is to design the counter so the design process needs to start where designs start - the truth table. Since this is a synchronous counter, the current state represented by the Q outputs of the FF will be the inputs to the truth table while the D inputs to the FF represent the next state of the counter and will be the output of the truth table. The truth table is also where you decide what 'self correcting' means. If the assignment does not require ripple carry in/out then don't worry about it (could it get you extra credit?) Preselectable DATA inputs can be handled as another layer of logic in the circuit so don't include these in the truth table. Then create a 5-input (4 Q & 1 up-down mode input) K-map for each D output. Minimize each K-map, draw the gates, and then your homework is done. Compare your design to the commercial design. If this is too difficult then maybe you could just hand in a photocopy of the commercial schematic.
     
  4. Stebven1231

    Stebven1231

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    Nov 1, 2012
    I started my work with truth table then continued with building the counter. I'd say It's okay so far. It works. But, there's one thing i do not really get yet. It's this "Then create a 5-input (4 Q & 1 up-down mode input) K-map for each D output."
    So, do you mean i should use one more variable is "M" besides Qd,Qc,Qb,Qa? Then how to use variable "M" in the truth table and also in K-Map?
     
  5. Harald Kapp

    Harald Kapp Moderator Moderator

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    Nov 17, 2011
    From Laplace's answer:
    The fifth variable is the mode pin for selecting count-up or count-down. You need to incorporate this mode into the equations (or truth tables) to allow mode selection.

    Harald
     
  6. Stebven1231

    Stebven1231

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    Nov 1, 2012
    I am still not sure how to design the circuit that's capable of counting up or down? I dealed separetly with counting up and down functions and made their own truth tables & K-maps. And now my counter theorically is capable of counting up or down. But how can i solve this problem with a simple switch?:D it's all i want to know. Maybe i am on a wrong way?
     
  7. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    In a D flip-flop, Q follows D.

    That means if your D flip flops have the values (Q) 0, 1, 1, and 0 and you're counting UP, then the D inputs need to be 0, 1, 1, 1.

    In the same case, if you're counting down, the D inputs must be 0, 1, 0, 1.

    So now we have 2 cases:

    M Q3 Q2 Q1 Q0 | D3 D2 D1 D0
    ------------------------------------------------
    0 0 1 1 0 | 0 1 1 1
    1 0 1 1 0 | 0 1 0 1

    There are 32 input states and 16 output states. Some of them may appear to be "don't care" states (because they are invalid), but you have a requirement that the device be self-correcting, so you need to consider how you'll handle them.

    Once you figure all of this out, how could you change M from 0 to 1 with a switch?
     
    Last edited: Nov 4, 2012
  8. Stebven1231

    Stebven1231

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    Nov 1, 2012
    What about the K-maps of each input of D ff? What shall i fill it with? I understand what's the next state if M=0 or M=1, but i dunno how to make the whole thing going on. What should I do next? I think a switch is needed to change the direction of counting, isn't it? I suppose M simbolizes a switch in this case. Like on my second schematics Fel_le symbolizes the up/down direction. : https://www.electronicspoint.com/at...ng-synchronous-counter-help-me-please-mmm.jpg How could you do this problem without a switch? I know I got many questions, but I haven't found anything about this issue that explains the whole proceed of how to design a counter like this on the internet. That's why I'm here. Anyway thanks everyone for your answers!
     
  9. (*steve*)

    (*steve*) ¡sǝpodᴉʇuɐ ǝɥʇ ɹɐǝɥd Moderator

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    Jan 21, 2010
    Read what I wrote again.

    Q follows D. The (partial) truth table I posted shows the mapping of the INPUTS of your logic (the mode and the Q outputs of your flip-flops) to the OUTPUTS of your logic (the input (D) of the flip-flops.

    What the truth table is describing the feedback from the Q outputs to the D inputs of the flip-flops to ensure they go to the correct state after the next clock pulse.
     
  10. Laplace

    Laplace

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    Apr 4, 2010
    Look at the commercial schematics you posted. How did they do it without a switch? Is the switch a part of the counter design? Suppose your up/down counter is intended for use in a digital PLL and the mode input is controlled by the phase comparator - no switch there!
     
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